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riscv: pmp: work around a QEMU bug

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The NAPOT mode isn't computed properly in qemu when the full address
range is covered. Let's hardcode the value that the qemu code checks
explicitly until the appropriate fix is applied to qemu itself.

For reference, here's the qemu patch:
https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00961.html

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-04-06 21:09:54 -04:00 • committed by Carles Cufí
commit f51d89df30
1 changed files with 10 additions and 0 deletions
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10
arch/riscv/core/pmp.c
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@ -327,6 +327,16 @@ void z_riscv_pmp_stackguard_prepare(struct k_thread *thread)
*/
set_pmp_entry(&index, PMP_R | PMP_W | PMP_X,
0, 0, PMP_M_MODE(thread));
#ifdef CONFIG_QEMU_TARGET
/*
* Workaround: The above produced 0x1fffffff which is correct.
* But there is a QEMU bug that prevents it from interpreting this
* value correctly. Hardcode the special case used by QEMU to
* bypass this bug for now. The QEMU fix is here:
* https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00961.html
*/
thread->arch.m_mode_pmpaddr_regs[index-1] = -1L;
#endif
/* remember how many entries we use */
thread->arch.m_mode_pmp_end_index = index;