riscv: pmp: work around a QEMU bug
The NAPOT mode isn't computed properly in qemu when the full address range is covered. Let's hardcode the value that the qemu code checks explicitly until the appropriate fix is applied to qemu itself. For reference, here's the qemu patch: https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00961.html Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
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@ -327,6 +327,16 @@ void z_riscv_pmp_stackguard_prepare(struct k_thread *thread)
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*/
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set_pmp_entry(&index, PMP_R | PMP_W | PMP_X,
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0, 0, PMP_M_MODE(thread));
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#ifdef CONFIG_QEMU_TARGET
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/*
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* Workaround: The above produced 0x1fffffff which is correct.
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* But there is a QEMU bug that prevents it from interpreting this
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* value correctly. Hardcode the special case used by QEMU to
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* bypass this bug for now. The QEMU fix is here:
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* https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00961.html
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*/
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thread->arch.m_mode_pmpaddr_regs[index-1] = -1L;
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#endif
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/* remember how many entries we use */
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thread->arch.m_mode_pmp_end_index = index;
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