riscv: pmp: new implementation
This is the core code to manage PMP entries with only the global entries initialisation for now. It is not yet linked into the build. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre
Carles Cufí
parent
3b990c9ddd
commit
2e66da3bc3
3 changed files with 377 additions and 0 deletions
107
arch/riscv/core/pmp.S
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107
arch/riscv/core/pmp.S
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/*
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* Copyright (c) 2022 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include "asm_macros.inc"
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#define CSR_PMPCFG_BASE 0x3a0
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#define CSR_PMPADDR_BASE 0x3b0
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/*
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* Prototype:
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*
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* void z_riscv_write_pmp_entries(unsigned int start, // a0
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* unsigned int end, // a1
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* bool clear_trailing_entries, // a2
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* ulong_t *pmp_addr, // a3
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* ulong_t *pmp_cfg) // a4
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*
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* Called from pmp.c to write a range of PMP entries.
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*
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* PMP registers are accessed with the csr instruction which only takes an
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* immediate value as the actual register. In order to avoid traversing
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* the whole register list, we use the start index to jump directly to the
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* location corresponding to the start of the wanted range. For this to work
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* we disallow compressed instructions so the update block sizes are easily
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* known (luckily they're all power-of-2's simplifying the code further).
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*
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* start < end && end <= CONFIG_PMP_SLOT must be true.
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*/
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GTEXT(z_riscv_write_pmp_entries)
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SECTION_FUNC(TEXT, z_riscv_write_pmp_entries)
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la t0, pmpaddr_store
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slli t1, a0, 4 /* 16-byte instruction blocks */
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add t0, t0, t1
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jr t0
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pmpaddr_store:
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.option push
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.option norvc
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.set _index, 0
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.rept CONFIG_PMP_SLOT
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lr t0, (RV_REGSIZE * _index)(a3)
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li t1, _index + 1
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csrw (CSR_PMPADDR_BASE + _index), t0
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beq t1, a1, pmpaddr_done
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.set _index, _index + 1
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.endr
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.option pop
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pmpaddr_done:
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/*
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* Move to the pmpcfg space:
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* a0 = a0 / RV_REGSIZE
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* a1 = (a1 + RV_REGSIZE - 1) / RV_REGSIZE
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*/
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la t0, pmpcfg_store
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srli a0, a0, RV_REGSHIFT
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slli t1, a0, 4 /* 16-byte instruction blocks */
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add t0, t0, t1
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addi a1, a1, RV_REGSIZE - 1
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srli a1, a1, RV_REGSHIFT
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jr t0
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pmpcfg_store:
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.option push
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.option norvc
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.set _index, 0
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.rept (CONFIG_PMP_SLOT / RV_REGSIZE)
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lr t0, (RV_REGSIZE * _index)(a4)
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addi a0, a0, 1
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csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), t0
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beq a0, a1, pmpcfg_done
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.set _index, _index + 1
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.endr
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.option pop
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pmpcfg_done:
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beqz a2, done
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la t0, pmpcfg_zerotail
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slli a0, a0, 2 /* 4-byte instruction blocks */
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add t0, t0, a0
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jr t0
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pmpcfg_zerotail:
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.option push
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.option norvc
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.set _index, 0
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.rept (CONFIG_PMP_SLOT / RV_REGSIZE)
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csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), zero
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.set _index, _index + 1
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.endr
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.option pop
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done: ret
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258
arch/riscv/core/pmp.c
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258
arch/riscv/core/pmp.c
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/*
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* Copyright (c) 2022 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Physical Memory Protection (PMP) is RISC-V parlance for an MPU.
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*
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* The PMP is comprized of a number of entries or slots. This number depends
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* on the hardware design. For each slot there is an address register and
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* a configuration register. While each address register is matched to an
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* actual CSR register, configuration registers are small and therefore
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* several of them are bundled in a few additional CSR registers.
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*
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* PMP slot configurations are updated in memory to avoid read-modify-write
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* cycles on corresponding CSR registers. Relevant CSR registers are always
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* written in batch from their shadow copy in RAM for better efficiency.
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*/
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#include <kernel.h>
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#include <kernel_internal.h>
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#include <linker/linker-defs.h>
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#include <pmp.h>
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#include <sys/arch_interface.h>
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#include <arch/riscv/csr.h>
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#define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(mpu);
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#define PMP_DEBUG_DUMP 0
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#ifdef CONFIG_64BIT
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# define PR_ADDR "0x%016lx"
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#else
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# define PR_ADDR "0x%08lx"
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#endif
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#define PMPCFG_STRIDE sizeof(ulong_t)
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#define PMP_ADDR(addr) ((addr) >> 2)
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#define NAPOT_RANGE(size) (((size) - 1) >> 1)
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#define PMP_ADDR_NAPOT(addr, size) PMP_ADDR(addr | NAPOT_RANGE(size))
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#define PMP_NONE 0
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static void print_pmp_entries(unsigned int start, unsigned int end,
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ulong_t *pmp_addr, ulong_t *pmp_cfg,
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const char *banner)
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{
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uint8_t *pmp_n_cfg = (uint8_t *)pmp_cfg;
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unsigned int index;
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LOG_DBG("PMP %s:", banner);
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for (index = start; index < end; index++) {
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LOG_DBG("%3d: "PR_ADDR" 0x%02x", index,
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pmp_addr[index],
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pmp_n_cfg[index]);
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}
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}
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static void dump_pmp_regs(const char *banner)
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{
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ulong_t pmp_addr[CONFIG_PMP_SLOT];
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ulong_t pmp_cfg[CONFIG_PMP_SLOT / PMPCFG_STRIDE];
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#define PMPADDR_READ(x) pmp_addr[x] = csr_read(pmpaddr##x)
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FOR_EACH(PMPADDR_READ, (;), 0, 1, 2, 3, 4, 5, 6, 7);
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#if CONFIG_PMP_SLOT > 8
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FOR_EACH(PMPADDR_READ, (;), 8, 9, 10, 11, 12, 13, 14, 15);
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#endif
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#undef PMPADDR_READ
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#ifdef CONFIG_64BIT
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pmp_cfg[0] = csr_read(pmpcfg0);
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#if CONFIG_PMP_SLOT > 8
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pmp_cfg[1] = csr_read(pmpcfg2);
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#endif
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#else
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pmp_cfg[0] = csr_read(pmpcfg0);
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pmp_cfg[1] = csr_read(pmpcfg1);
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#if CONFIG_PMP_SLOT > 8
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pmp_cfg[2] = csr_read(pmpcfg2);
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pmp_cfg[3] = csr_read(pmpcfg3);
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#endif
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#endif
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print_pmp_entries(0, CONFIG_PMP_SLOT, pmp_addr, pmp_cfg, banner);
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}
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/**
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* @brief Set PMP shadow register values in memory
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*
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* Register content is built using this function which selects the most
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* appropriate address matching mode automatically. Note that the special
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* case start=0 size=0 is valid and means the whole address range.
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*
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* @param index_p Location of the current PMP slot index to use. This index
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* will be updated according to the number of slots used.
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* @param perm PMP permission flags
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* @param start Start address of the memory area to cover
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* @param size Size of the memory area to cover
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* @param pmp_addr Array of pmpaddr values (starting at entry 0).
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* @param pmp_cfg Array of pmpcfg values (starting at entry 0).
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* @param index_limit Index value representing the size of the provided arrays.
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* @return true on success, false when out of free PMP slots.
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*/
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static bool set_pmp_entry(unsigned int *index_p, uint8_t perm,
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uintptr_t start, size_t size,
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ulong_t *pmp_addr, ulong_t *pmp_cfg,
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unsigned int index_limit)
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{
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uint8_t *pmp_n_cfg = (uint8_t *)pmp_cfg;
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unsigned int index = *index_p;
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bool ok = true;
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__ASSERT((start & 0x3) == 0, "misaligned start address");
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__ASSERT((size & 0x3) == 0, "misaligned size");
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if (index >= index_limit) {
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LOG_ERR("out of PMP slots");
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ok = false;
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} else if ((index == 0 && start == 0) ||
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(index != 0 && pmp_addr[index - 1] == PMP_ADDR(start))) {
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/* We can use TOR using only one additional slot */
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pmp_addr[index] = PMP_ADDR(start + size);
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pmp_n_cfg[index] = perm | PMP_TOR;
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index += 1;
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} else if (((size & (size - 1)) == 0) /* power of 2 */ &&
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((start & (size - 1)) == 0) /* naturally aligned */) {
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pmp_addr[index] = PMP_ADDR_NAPOT(start, size);
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pmp_n_cfg[index] = perm | (size == 4 ? PMP_NA4 : PMP_NAPOT);
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index += 1;
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} else if (index + 1 >= index_limit) {
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LOG_ERR("out of PMP slots");
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ok = false;
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} else {
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pmp_addr[index] = PMP_ADDR(start);
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pmp_n_cfg[index] = 0;
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index += 1;
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pmp_addr[index] = PMP_ADDR(start + size);
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pmp_n_cfg[index] = perm | PMP_TOR;
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index += 1;
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}
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*index_p = index;
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return ok;
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}
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/**
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* @brief Write a range of PMP entries to corresponding PMP registers
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*
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* PMP registers are accessed with the csr instruction which only takes an
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* immediate value as the actual register. This is performed more efficiently
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* in assembly code (pmp.S) than what is possible with C code.
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*
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* Requirement: start < end && end <= CONFIG_PMP_SLOT
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*
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* @param start Start of the PMP range to be written
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* @param end End (exclusive) of the PMP range to be written
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* @param clear_trailing_entries True if trailing entries must be turned off
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* @param pmp_addr Array of pmpaddr values (starting at entry 0).
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* @param pmp_cfg Array of pmpcfg values (starting at entry 0).
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*/
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extern void z_riscv_write_pmp_entries(unsigned int start, unsigned int end,
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bool clear_trailing_entries,
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ulong_t *pmp_addr, ulong_t *pmp_cfg);
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/**
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* @brief Write a range of PMP entries to corresponding PMP registers
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*
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* This performs some sanity checks before calling z_riscv_write_pmp_entries().
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*
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* @param start Start of the PMP range to be written
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* @param end End (exclusive) of the PMP range to be written
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* @param clear_trailing_entries True if trailing entries must be turned off
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* @param pmp_addr Array of pmpaddr values (starting at entry 0).
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* @param pmp_cfg Array of pmpcfg values (starting at entry 0).
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* @param index_limit Index value representing the size of the provided arrays.
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*/
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static void write_pmp_entries(unsigned int start, unsigned int end,
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bool clear_trailing_entries,
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ulong_t *pmp_addr, ulong_t *pmp_cfg,
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unsigned int index_limit)
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{
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__ASSERT(start < end && end <= index_limit &&
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index_limit <= CONFIG_PMP_SLOT,
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"bad PMP range (start=%u end=%u)", start, end);
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/* Be extra paranoid in case assertions are disabled */
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if (start >= end || end > index_limit) {
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k_panic();
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}
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if (clear_trailing_entries) {
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/*
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* There are many config entries per pmpcfg register.
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* Make sure to clear trailing garbage in the last
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* register to be written if any. Remaining registers
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* will be cleared in z_riscv_write_pmp_entries().
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*/
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uint8_t *pmp_n_cfg = (uint8_t *)pmp_cfg;
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unsigned int index;
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for (index = end; index % PMPCFG_STRIDE != 0; index++) {
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pmp_n_cfg[index] = 0;
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}
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}
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print_pmp_entries(start, end, pmp_addr, pmp_cfg, "register write");
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z_riscv_write_pmp_entries(start, end, clear_trailing_entries,
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pmp_addr, pmp_cfg);
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}
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/*
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* This is used to seed thread PMP copies with global m-mode cfg entries
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* sharing the same cfg register. Locked entries aren't modifiable but
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* we could have non-locked entries here too.
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*/
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static ulong_t global_pmp_cfg[1];
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/* End of global PMP entry range */
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static unsigned int global_pmp_end_index;
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/**
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* @Brief Initialize the PMP with global entries on each CPU
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*/
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void z_riscv_pmp_init(void)
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{
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ulong_t pmp_addr[4];
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ulong_t pmp_cfg[1];
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unsigned int index = 0;
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/* The read-only area is always there for every mode */
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set_pmp_entry(&index, PMP_R | PMP_X | PMP_L,
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(uintptr_t)__rom_region_start,
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(size_t)__rom_region_size,
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pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
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write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
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#ifdef CONFIG_SMP
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/* Make sure secondary CPUs produced the same values */
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if (global_pmp_end_index != 0) {
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__ASSERT(global_pmp_end_index == index, "");
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__ASSERT(global_pmp_cfg[0] == pmp_cfg[0], "");
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}
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#endif
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global_pmp_cfg[0] = pmp_cfg[0];
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global_pmp_end_index = index;
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if (PMP_DEBUG_DUMP) {
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dump_pmp_regs("initial register dump");
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}
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}
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12
arch/riscv/include/pmp.h
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12
arch/riscv/include/pmp.h
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@ -0,0 +1,12 @@
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/*
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* Copyright (c) 2022 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef PMP_H_
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#define PMP_H_
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void z_riscv_pmp_init(void);
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#endif /* PMP_H_ */
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