Commit graph

20 commits

Author SHA1 Message Date
Nicolas Pitre
1f4b5ddd0f riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00
Øyvind Rønningstad
c760ca02eb arch: Put intlist.ld into Cmake
Remove from linker.ld

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-05-20 22:28:28 -04:00
Øyvind Rønningstad
f2a1572ac2 cmake: Add function for adding snippets to the linker file
Allows snippets to be placed in different locations:
 - The noinit, rwdata and rodata output sections
 - Two different locations for placing custom output sections,
   one location for RAM and another for all other sections.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2019-05-20 22:28:28 -04:00
Filip Kokosinski
e0a825003d riscv32: use device tree defines in linker
Delete memory-related configs from defconfig and use device tree based
macros in general riscv32 linker script instead of Kconfig ones.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-05-10 10:34:31 -05:00
Kumar Gala
10f2bdfc57 linker: riscv32: Fix .riscv.attributes orphan sections warning
Add similar fix to riscv32 linker scripts that we have on ARM for
.riscv.attributes section.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-15 12:37:21 -05:00
Nathaniel Graff
0289a410ba riscv32: linker: Link .srodata section
Building tests/kernel/common/kernel.common with the new crosstools
SDK-ng resulted in an orphan short read-only data section. Fix this by
adding the .srodata section to the RISC-V linker script.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-23 23:28:03 -05:00
Andrew Boie
506f15c381 interrupts: simplify position of sw ISR table
We now place the linker directives for the SW ISR table
in the common linker scripts, instead of repeating it
everywhere.

The table will be placed in RAM if dynamic interrupts are
enabled.

A dedicated section is used, as this data must not move
in between build phases.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Vitaly Gaiduk
abdb8785cb linker: riscv: Disable creating ROM domain by config option.
Patch is useful for RISCV platforms which can not provide ROM memory.
Switching CONFIG_XIP to "n" disables allocating ROM region.

Signed-off-by: Vitaly Gaiduk <vitaly.gaiduk@cloudbear.ru>
2018-11-03 23:00:01 -04:00
Daniel Leung
6600c64331 linker: warn about orphan sections
(Previous patch set was reverted due to issue with priv_stack.
 Resubmitting after fixing the faults caused by priv_stack.noinit
 not at the end of RAM.)

This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.

Relates to #5534.

Fixes #10473, #10474, #10515.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 16:11:34 -04:00
Daniel Leung
1134e59bd2 linker: allow SoC to insert linker script fragments
This allows the SoC to specify some additional linker script
fragments into the bss, data and read-only data sections.

For example, the Cypress PSOC6 has a few input sections that
must be put into bss and data sections. Without specifying
these in the linker script, they are consider orphan sections
and the placement is based on linker heuristic which is
arbitrary.

POSIX is not supported as the main linker script is
provided by the host system's binutils and we have no control
over it. Also, currently Xtensa SoCs have their own linker
scripts so there is no need to this feature.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 16:11:34 -04:00
Anas Nashif
1d0136ef3b Revert "linker: allow SoC to insert linker script fragments"
This reverts commit 2fed930f4e.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 12:14:04 -04:00
Anas Nashif
0d4b5daeaa Revert "linker: warn about orphan sections"
This reverts commit 8ce758a8ff.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 12:14:04 -04:00
Daniel Leung
8ce758a8ff linker: warn about orphan sections
This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.

Relates to #5534.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Daniel Leung
2fed930f4e linker: allow SoC to insert linker script fragments
This allows the SoC to specify some additional linker script
fragments into the bss, data and read-only data sections.

For example, the Cypress PSOC6 has a few input sections that
must be put into bss and data sections. Without specifying
these in the linker script, they are consider orphan sections
and the placement is based on linker heuristic which is
arbitrary.

POSIX is not supported as the main linker script is
provided by the host system's binutils and we have no control
over it. Also, currently Xtensa SoCs have their own linker
scripts so there is no need to this feature.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Nathaniel Graff
15516ed0ef linker: riscv: Relocate .eh_frame symbol
The .eh_frame symbol was causing __data_rom_start to contain the wrong
offset into the ROM, resulting in corrupt data copied into RAM by
_data_copy(). Fix by placing the .eh_frame in the .text section as is
done in include/arch/x86/linker.ld

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-07-30 13:38:31 -05:00
Sebastian Bøe
347f9a0a2d cmake: LD: Specify the entry point in the linker scripts
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.

This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command

ENTRY(CONFIG_KERNEL_ENTRY)

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-07-03 17:18:14 -04:00
Anas Nashif
397d29db42 linker: move all linker headers to include/linker
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-18 09:24:04 -05:00
Andrew Boie
bd69c3bdf0 riscv32: enable gen_isr_tables mechanism
Change-Id: Ia09d9a4d3412424dcbb25db829059a0714d81214
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:17 +00:00
Leandro Pereira
570634a259 kernel: Add OpenOCD support
In order for OpenOCD to have a high-level view of an RTOS, it uses the
GDB protocol to obtain symbols from the system.

The GDB protocol, however, does not allow obtaining fields from
structures directly, and hardcoding offsets is not only brittle (due to
possibly different architectures or changes in the code), it's also
infeasible considering Zephyr is highly-configurable and parts of key
structs can be compiled in or out.

Export an array with offsets for these key structs. Also add a version
element in that array to allow changes in those structs.

Change-Id: I83bcfa0a7bd57d85582e5ec6efe70e1cceb1fc51
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-02-11 03:57:19 +00:00
Jean-Paul Etienne
47e2f4e3d7 riscv32: added a generic linker script for the riscv32 platform
Added a linker script that shall be common to most riscv SOCs.
Linker script also accounts for execution in place in ROM, when
CONFIG_XIP is set.

Nonetheless, riscv32 SOCs (like pulpino) requiring a different
system layout can still define their own linker script.

Change-Id: I3ad670446d439772c29a8204e307ac79643dc650
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-03 19:20:52 +01:00
Renamed from include/arch/riscv32/riscv32-qemu/linker.ld (Browse further)