Renamed two functions and a macro to use more generic names,
removing chip-specific identifiers.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Move register definitions from chip_chipregs.h into espi_it8xxx2.c to
make the driver more adaptable to different SoCs.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
1. Add it51526bw SoC variant to it51xxx SoC series.
2. Create the .dtsi file with adjusted flash size for 512Kb (default = 1M).
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Previously, the RAM code size was limited to 1K, causing issues when the
code exceeded this limit. This update modifies the implementation to
support RAM code sizes up to 4K
test: zephyrproject/zephyr/tests/drivers/flash/common --> pass
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Use generic name for structure in driver instead of specific chip name
for better compatibility.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Some files should be separated from the common folder to
each soc folder for future expansion of the chip.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The chip requires a successful sleep entry to change the PLL sequence.
By default, the IT8XXX2 chip enables the I2C0 alternate function, which
can cause the clock/data lines to meet the start condition, preventing
EC from entering sleep mode.
This commit disables the I2C0 alternate function before executing the
PLL sequence change to ensure that the EC can enter sleep mode
successfully.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
If a board defined CONFIG_FLASH_LOAD_OFFSET to a non-zero value,
enabling CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE generated a linker
error because when trying to move the location counter backwards.
Fixed by allocating the JTAG section within the deined ROM region.
Signed-off-by: Keith Short <keithshort@google.com>
PM, PM_DEVICE etc should be enabled by the application/samples, not the
board.
Add a config to default to custom policy for the board though since
there's one defined at soc level.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.
To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.
`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This change disables USB debug path at default, in order to prevent SoC
from entering debug mode when there is signal toggling on GPH5/GPH6.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
custom arch_cpu_idle and arch_cpu_atomic_idle implementation was done
differently on different architectures. riscv implemented those as weak
symbols, xtensa used a kconfig and all other architectures did not
really care, but this was a global kconfig that should apply to all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
After flashed EC image, we needed to manually press the reset button
on it8xxx2_evb. Now, without pressing the button, we can disable
debug mode and trigger a watchdog hard reset for running tests.
After flash EC, running below tests can pass (without pressing the button):
west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p always -b it8xxx2_evb tests/kernel/fatal/exception
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Place zephyr library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libzephyr.a: +16974 bytes -608ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place kernel library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libkernel.a: +8941 bytes -649ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place serial library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libdrivers__serial.a: +2282 bytes -226ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Currently iterable sections as per the documentation are added with
zephyr_linker_sources(SECTIONS ...) after bss/noinit.
This commit allows putting sections after common-rom.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit introduces support for an alternate linking method in the
LLEXT subsystem, called "SLID" (short for Symbol Link Identifier),
enabled by the CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID Kconfig option.
SLID-based linking uses a unique identifier (integer) to identify
exported symbols, instead of using the symbol name as done currently.
This approach provides several benefits:
* linking is faster because the comparison operation to determine
whether we found the correct symbol in the export table is now an
integer compare, instead of a string compare
* binary size is reduced as symbol names can be dropped from the binary
* confidentiality is improved as a side-effect, as symbol names are no
longer present in the binary
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The ILM_MAX_SIZE of different chip variants can be declared in the
Kconfig of the respective variant.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Using the SOC_IT8XXX2_REG_SET_V2 instead of constantly adding new
variants of the IT82XX2 SoC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Prevent the CPU from entering deep doze mode when JTAG debug is enabled.
Additionally, The CPU address from 0x80000800 to 0x800008FF should be
reserved for JTAG debug usage. This commit reserves the area from the end
of the reset section to 0x800008FF if JTAG debug is enabled.
Tested with:
- west build -p always -b it82xx2_evb samples/hello_world/
-DCONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE=y
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Variant chip has different USBPD HW PHY, so FW needs
to apply different downstream CONFIG settings based on
the PHY version.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
