Add `hifive_unmatched//s7` (earlier selected by default, using
`hifive_unmatched`) and `hifive_unmatched//u74` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This revert the idea of 3fa7d78 from #78845.
The 3rd level IRQ APIs won't compile when
CONFIG_3RD_LEVEL_INTERRUPT_BITS=0.
Updated testcase accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Amend the filtering so that the normal mem_map (with exec) test
is not going to run on Intel Audio DSP SoCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With the rename of intel_adsp/ace30_ptl to intel_adsp/ace30/ptl,
the "sim" variant no longer inherit the base configuration. So
make a copy of the .conf file to explicitly target the sim
variant.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Obviously, everyone knows that there are 8 bits per byte, so
there isn't a lot of magic happening, per se, but it's also
helpful to clearly denote where the magic number 8 is referring
to the number of bits in a byte.
Occasionally, 8 will refer to a field size or offset in a
structure, MMR, or word. Occasionally, the number 8 will refer
to the number of bytes in a 64-bit value (which should probably
be replaced with `sizeof(uint64_t)`).
For converting bits to bytes, or vice-versa, let's use
`BITS_PER_BYTE` for clarity (or other appropriate `BITS_PER_*`
macros).
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Added empty fp register structs for ARM combinations not handled,
i.e. any ARM without a fpu.
Signed-off-by: Lars-Ove Karlsson <lars-ove.karlsson@iar.com>
Adjust default number of test samples which is based on SRAM size.
Test is using 8*TIMER_TEST_SAMPLES and with previous defaults for
the device with 64k RAM it was using 56k of test data leaving only
8k RAM and that was easily not enough. Adjust conditions to
take less samples when SRAM_SIZE is equal to the threshold.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
In ARM architectures the entry_cpu_exception_extend calls
svc #0 when trying to generate a `K_ERR_CPU_EXCEPTION`, however
z_arm_svc calls z_do_oops with a stack frame only, and gets the
reason from `r0`. This means that the test working was just lucky
and running it with another compiler (or setting the value of r0
before the svc #0 call, made the test fail).
Cortex-A/R 32-bit architectures was doing a BKPT, this works better
but will not be a hard exception when debugger is attached.
I switched all the Cortex 32-bits to the ARM specified undefined
instruction.
Also RISC-V has a designated unimp instruction that should be used to
guarantee trap.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
For some weird reasons, enabling ICOUNT would result in some
tests crashing QEMU. So disable ICOUNT.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
sqrtf() is used for floats but the argument and resulting
variable are both doubles. LLVM would complain about
implicit conversion from float to double. So use sqrt()
instead as it is used with doubles.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commits defines the `#power-domain-cells` properties for fakedomain
nodes in the HiFive Unmatched devicetree overlay file.
Without this change, this tests fails to build for the `hifive_unmatched`
Zephyr target.
Fixes#80503.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
What is changed?
- Added a new mps3 board an552 for the soc corstone300.
The qualifier to build/run application with board mps3/an552 is
`mps3/corstone300/an552` for secure and
`mps3/corstone300/an552/ns` for non-secure.
- Added FVP variant to enable FVP testing with corstone300
and it uses the ARM FVP `FVP_Corstone_SSE-300_Ethos-U55`.
The qualifier to build/run application with FVP is
`mps3/corstone300/fvp` for secure and
`mps3/corstone300/fvp/ns` for non-secure.
- Note: the qualifier to build/run application with board mps3/an547
is now changed to
`mps3/corstone300/an547` for secure and
`mps3/corstone300/an547/ns` for non-secure.
How is it changed?
- Moved common code from mps3/an547 to corstone300.
- Renamed soc for an547 to corstone300 and added
a new soc corstone300/an552.
Why do we need this change?
- This enables FVP support and testing for corstone300.
- SOC/qualifier for mps3/an547 was renamed to reduce code redundancy
- A separate FVP variant was added for AN552 because, the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps3/corstone300/fvp` should be used when testing
AN552 with FVP and `arm/mps3/corstone300/an552` should be used when
testing with AN552 FPGA.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Some devices may belong to >1 power domain, so with the current design
this is something not possible to describe. It's worth to note that
Linux also uses the `power-domains` naming scheme, not `power-domain`.
This patch also introduces `power-domain-names` so that each entry in
`power-domains` can be given a name if needed. `#power-domain-cells`
is now required as well.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The test_k_mem_map_unmap test requires some free physical pages
to work correctly. On qemu_x86_tiny, the physical memory is
artificially limited to test demand paging, which is 320KB as
of writing of this commit message. We also reserve 128KB of
physical memory as swapping area. And we do pin quite lot of
text and data (relatively speaking) in memory. There is not
much memory left for the test. So lower the amount of reserved
memory for paging to leave some pages for the test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
What is the changed?
CPU affinity test for SMP cores will now cover a change in ROM offset.
How is it changed?
Add a new testcase section with ROM offset set to something other than
the default 0.
Why is it change?
There is no test to cover the issue reported in #76182 and the cpu
affinity test is the closest to test the issue. Adding a new testcase
will makes sure there is no breaking change in the future.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Add dedicated interrupt lines for nrf54h20_cpuppr. Similar exception
was already added to nrf54l15_flpr: 8742e2476.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This needs special treatment because the TEST_MEM_MAP section
is placed at the end. Since there is code in TEST_MEM_MAP,
rimage thinks the whole text section spans from .text to
end of TEST_MEM_MAP, which overlaps .data and others, so
it complains. Skip the execution test to avoid this issue.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The board has been renamed from intel_adsp/ace30_ptl to
intel_adsp/ace30/ptl. So the corresponding board only configs
for tests also need to renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Unlike a normal IRQ, a multilevel IRQ can't be incremented by
simply `irq++`, as that would always increment the L1 of a IRQ,
regardless of its level. A function that understands the level
for which the IRQ operates in is required.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Test multilevel-irq APIs with interrupt number generated from
the devicetree to make sure that they work in sync.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The following Kconfigs are always enabled on `qemu_riscv32`:
- CONFIG_MULTI_LEVEL_INTERRUPTS
- CONFIG_2ND_LEVEL_INTERRUPTS
- CONFIG_RISCV_PRIVILEGED
No need to enable/filter for them in the testcase.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The multilevel IRQ APIs tests are currently cordoned off by
`CONFIG_MULTI_LEVEL_INTERRUPTS` compiler switch, do this more
cleanly by moving it to another file and use cmake for that
instead.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The IRQ for level 1 and above is incremented by 1 when encoded
with Zephyr's multilevel IRQ scheme, so it should be
decremented by 1.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This is in preparation for adding another SoC where qemu_xtensa
is no longer valid choice. So use qemu_xtensa/dc233c as it is
the same as the old qemu_xtensa.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Current clocks configuration for the platform makes it impossible
to pass the IDLE_EVENT_STATS_PRECISION check. This is to be addressed
in the future.
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
This case fails to build on boards having APIC TSC timer enabled.
This change is needed after moving APIC TSC timer support from
apic_timer.c to apic_tsc.c.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Up until now, the `__thread` keyword has been used for declaring
variables as Thread local storage. However, `__thread` is a GNU
specific keyword which thus limits compatibility with other
toolchains (for instance IAR).
This PR intoduces a new macro `Z_THREAD_LOCAL` which expands to the
corresponding C11, C23 or C++11 standard keyword based on the standard
that is specified during compilation, else it uses the old `__thread`
keyword.
Signed-off-by: Daniel Flodin <daniel.flodin@iar.com>
For code clarity, remove unnecessary `return` statements
in functions with a void return type they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit re-enables the following platforms for the
`kernel.common.stack_sentinel` test:
* `hifive1`
* `m2gl025_miv`
These platforms working correctly after Renode was upgraded to 1.15.2 in
the CI.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Few tests with wrongly names platforms. This section is now being
verified for correctness like all others.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
- Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the
devicetree
- Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to
be able to encode the L2 IRQs.
- Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024)
Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase
accordingly, so that it won't overflow the configured bits.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit excludes the `m2gl025_miv` platform from running the
`kernel.common.stack_sentinel` test. It experiences the same issue as
`hifive1`, which was described in issue #66070.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This provides memory mappings with the ability to be initialized in their
paged-out state and be paged in on demand. This is especially nice for
anonymous memory mappings as they no longer have to allocate all memory
at mem_map time. This also allows for file mappings to be implemented by
simply providing backing store location tokens.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
