For OpenVega board, in the case of the Zero Riscy core,
the flash partition used for the code and data is the
M0 ARM core's 256KB flash region. This is closest to
the RISC core.
The m0_flash node defines where the interrupt vector
is located for the Zero Riscy core, and one needs to
restrict the application so its interrupt vector is
placed accordingly.
Fixes: 34b0516466 ("boards: riscv32: rv32m1_vega:
enable MCUboot for ri5cy core")
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
It is expressed that the BOARD depends on whether NONSECURE is enabled
or not. But it is the other way around. Depending on the selected
board, it may or may not be possible to enable/disable NONSECURE.
The dependency is going in the wrong direction, this reversed edge is
observed to be able to create a cycle in the dependency graph.
Fix the dependency by removing it.
It is left as future work to enforce that enabling/disabling NONSECURE
is done in a way that is compatible with selecting
BOARD_NRF9160_PCA10090 vs BOARD_NRF9160_PCA10090NS.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The "{d,i}ccm" nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are {d,i}ccm.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The true mmio-sram nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are SRAM.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add SPI support for stm32mp157c_dk2 board. If SPI is selected, SPI4
(Arduino connector compatible SPI) and SPI5 (on front 2x20 GPIO
expander) will be enable by default on stm32mp157c_dk2 board.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
(This could not be triggered in the nrf52_bsim yet,
so just so it is fixed for the future)
Properly handle converting back and forth from absolute to HW
time when either of those is set to TIME_NEVER
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
System clock for m4 core was set to same clock as m7 core.
This is wrong as m4 its value is actually based on clock frequency
value after D1CPRE (sys_d1cpre_ck) divided per HPRE value, 200MHz in
current case.
This also matches the max clock speed for the m4 core (200MHz)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
cores
In order to prevent potential misconfiguration set the clock setting,
which impacts both cores, under board.defconfig file which is used
by both core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Adapted from similar code in the x86_64 port.
Useful when debugging boot problems on actual x86
hardware if a JTAG isn't handy or feasible.
Turn this on for qemu_x86.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Write all the desired values in the debug control flag.
Initally we were oring it, but this variable does not have
the expected initial values as it also depends on fuse
programming settings, therefore we dont have console.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Allow the user to use software slave select instead of the
hardware pin, in order to free the related GPIO and avoid
unwanted SS triggering on the hardware pin. The default SS
is still the hardware pin.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
ARC nSIM simulates pretty much any modern ARC core,
moreover it emulates a lot of different core features so
it is possible to play with them even wo real hardware.
Thus we add yet another ARC core family to be used on simulated
nSIM board.
For now it's just a basic configuration with ARC UART for
smoke-testing of Zephyr on ARC HS CPUs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The ARC HS is a family of high performance CPUs from Synopsys
capable of running wide range of applications from heavy DPS
calculation to full-scale OS.
Still as with other ARC cores ARC HS might be tailored to
a particular application.
As opposed to EM cores ARC HS cores always have support of unaligned
data access and by default GCC generates such a data layout with
so we have to always enable unaligned data access in runtime otherwise
on attempt to access such data we'd see "Unaligned memory exception".
Note we had to explicitly mention CONFIG_CPU_ARCEM=y in
all current defconfigs as CPU_ARC{EM|HS} are now parts of a
choice so we cannot simply select ether option in board's Kconfig.
And while at it change "-mmpy-option" of ARC EM to "wlh1"
which is the same as previously used "6" but matches
Programmer's Reference Manual (PRM) and is more human-friendly.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This will give us a possibility to check unaligned read/write support
in simulation.
Note nSIM with S(ecure)EM (with secure option) doesn't support that
mode in HW.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Musca B1 has 2 x 2MB embedded flash memories (eFlash). The flash
memories are connected to the AHB Master Expansion “Code Interface”.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This property is only declared in bindings/spi/nordic,nrf-spis.yaml ('s'
for 'slave'), not in bindings/spi/nordic,nrf-spi.yaml.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add the link between the i2c and the arduino connector,
here i2c5.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
I2C5 are used by arduino connector.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
We generated a define for each instance to convey its existance of the
form:
#define DT_<COMPAT>_<INSTANCE> 1
However we renamed all other instance defines to be of the form
DT_INST_<INSTANCE>_<FOO>. To make things consistent we now generate a
define of the form:
#define DT_INST_<INSTANCE>_<COMPAT> 1
We also now deprecate the DT_<COMPAT>_<INSTANCE> form and fixup all uses
to use the new form.
Fixes: #17650
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As we now have PPP support, use more generic "serial-net" string instead
of "slip" when setting what kind of networking the board supports.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Expose eSPI block with interrupts enabled for channel 0 & 1
eSPI handshake has been tested using espi driver sample app
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
