Fix nucleo_f411re default configuration by deactivating I2C support.
Additionally fix wrong comment and end of file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update a number of boards that have arduino_gpio and arduino_i2c
support in their dts files to show that they support that in the
board.yaml file. This allows coverage on several shield tests that
utilize the tags 'arduino_gpio' and 'arduino_i2c'.
Exlucde stm32mp157c_dk2 from some of the samples right now since the
connector on the board doesn't support A2/A3. Also remove the duplicate
of exluding disco_l475_iot1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the NXP FRDM-K82F development board. This board
features an NXP MK82FN256VLL15 CPU, a user RGB LED and two buttons,
two 32 Mb QSPI flashes, Arduino R3 compatible headers, and a FlexIO
header.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Since lpuart4 is enabled by default on mimxrt1015_evk but not configured
in the device tree, this leads to a build error after adding the
instance to the lpuart driver. Adjust the mimxrt1015_evk to be the same
as other mimxrt evk boards and enable the lpuart only if BT_UART is
enabled.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
This patch is to add support for the Pico-Pi board which has an i.MX7D
Dual SoC.
The Zephyr is running on the Cortex M4 core and the following features
were validated on this board:
* UART: Zephyr console
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
We should use OpenOCD from the latest Zephyr SDK as opposed to using TI
OpenOCD.
There is a known issue with the current release (0.10.2) of the SDK in
how it resets the network processor, but we can deal with it
subsequently.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Moved arduino_spi to spi2
Set sck-pin in arduino_spi correctly as pin 25
Moved disabled spi0 miso pin assignment to pin 28
Signed-off-by: Nick Ward <nick.ward@setec.com.au>
This commit adds a note alluding to the fact that these two boards are
primarily included for use with QEMU, but have been tested on actual
hardware as well where appropriate.
Signed-off-by: Kevin Townsend <kevin@ktownsend.com>
This commit adds a note alluding to the fact that these two boards are
primarily included for use with QEMU, but have been tested on actual
hardware as well where appropriate.
Signed-off-by: Kevin Townsend <kevin@ktownsend.com>
MEC1501 RTOS timer internal counter is on the 32KHz clock domain.
The register interface is on the AHB clock. When the timer is started
hardware synchronizes to the next 32KHz clock edge resulting is a
variable delay moving the value in the preload register into the
count register. The maximum delay is one 32KHz clock period (30.5 us).
We work-around this delay by checking if the timer has been started
and not using the count value which is still 0. Instead we state zero
counts have elapsed.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
While trying out the hello_world sample built for QEMU, I was expecting
the sample app to exit and I'd return to a command prompt. Nope. You
need to exit QEMU manually, so add that step to the sample instructions.
Looking around, there are more uses of QEMU like this that could use
this added step after running the sample app.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
There are a few non-PNG (JPEG and WebP) files that are being
name as PNG files. This causes pdflatex/latexmk to fail due
to them not actually being PNG files. So rename those files
with correct extensions and update the RST files.
Also converted the WebP file in JPEG as PDFLatex cannot parse
WebP image.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The MSI PLL mode has been disabled but can be used since LSE is
populated on disco_l475_iot1 board. This is requested to enable
USB device controller support.
Fixes#18717
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Instead of having a mix of west and CMake/ninja instructions for
building and flashing, document it using only west. This will help
clarify that west is the default build tool in Zephyr and should also
reduce confusion over what tool to use.
Note that the biggest change is changing the default in
doc/extensions/zephyr/application.py for :tool:, from all to west.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This commit enables the pullup on CAN0_RX pin (PORTB 19).
The pullup ensures that the CAN controller initializes even
without a transceiver connected.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
now we use hex file instead of elf file for flash command as
PR #17822 suggested, so enable BUILD_OUTPUT_HEX by default for
board sam_e70_xplained.
Fixes: #18181.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Selection of the HFRCO causes the SOC to stay at its power-up frequency
of 19 MHz. Switch to the HFXO to use the configured frequency.
Closes#17630
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This adds support for SARA-U2 modems. They have different timings on
the PWR_ON pin, don't support AT+CESQ and require a manual GPRS
connection setup.
The VINT pin is used as a more reliable and faster way to power on the
modem.
Based on work by Göran Weinholt <goran.weinholt@endian.se>
Signed-off-by: Michael Scott <mike@foundries.io>
In nRF9160 the reset pin is a dedicated one, it cannot be configured
as a regular GPIO pin, so this option should not be presented to users
building for this SoC, to not generate confusion.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This driver makes use of the nRF RNG peripheral, so it can be used only
for SoCs that are equipped with one, and not all nRF SoCs are.
The option enabling the driver should then depend on `HAS_HW_NRF_RNG`,
which indicates the presence of this peripheral in a given SoC.
This patch removes also entries disabling this driver in default
configurations for nRF9160 SoC, as these were needed only because
of the invalid dependency of the ENTROPY_NRF5_RNG option.
A minor adjustment of Kconfig files of the nrf52_bsim board was
required as well, so that this board's configuration can properly
handle this corrected dependency.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In order to increase code coverage, we force building a Secure
Firmware image by default (i.e. with option
CONFIG_TRUSTED_EXECUTION_SECURE set), when building for
mps2_an521 board. CONFIG_TRUSTED_EXECUTION_SECURE enables
compiling-in all TrustZone-related code in the tree, that is,
all ARM-specific code inside #ifdef CONFIG_ARM_SECURE_FIRMWARE.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add support for driving the on-board LEDs present on the NXP TWR-KE18F
development board using FlexTimer (FTM) PWM modulation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The number of MPU regions appears to be 16 instead of 8,
so we fix that in the board .dts files.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Same deal as in commit a84ded74ea ("dts: Replace status = "ok" with
status = "okay""), for newly introduced stuff.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Route these to the equivalent pins for RXD1 and TXD1 on the Arduino
Mega.
Note that uart0 is routed to the debug probe IC on the nRF9160
DK, and uart1 is routed to where the RXD0 and TXD0 Arduino pins are on
the DK. This makes RXD1/TXD1 a logical place to put these UART pins,
since the header layout for the DK board matches the Arduino mega.
This is also necessary to keep some downstream code compiling which
needs to enable the UART2 but doesn't have a good place to put these
pins, since the new DTS parser is enforcing that all required
properties (like tx-pin and rx-pin in this case) are set for nodes
with status = "okay".
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Enable Mailbox support on 96Boards Avenger96 board. This will help
communicating to CortexA7 core.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Add onboard LEDs on 96Boards Avenger96 board. There are 4 user LEDs
on this board but only 3 are enabled. This is due to the fact that
LED0 is connected to unavailable PortZ. Hence, LED0 is ignored and
remaining LEDs are enabled starting from index 0.
Once PortZ is added, this will be fixed.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
It is expressed that the BOARD depends on whether NONSECURE is enabled
or not. But it is the other way around. Depending on the selected
board, it may or may not be possible to enable/disable NONSECURE.
The dependency is going in the wrong direction, this reversed edge is
observed to be able to create a cycle in the dependency graph.
Fix the dependency by removing it.
It is left as future work to enforce that enabling/disabling NONSECURE
is done in a way that is compatible with selecting
BOARD_NRF9160_PCA10090 vs BOARD_NRF9160_PCA10090NS.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The true mmio-sram nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are SRAM.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add SPI support for stm32mp157c_dk2 board. If SPI is selected, SPI4
(Arduino connector compatible SPI) and SPI5 (on front 2x20 GPIO
expander) will be enable by default on stm32mp157c_dk2 board.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
System clock for m4 core was set to same clock as m7 core.
This is wrong as m4 its value is actually based on clock frequency
value after D1CPRE (sys_d1cpre_ck) divided per HPRE value, 200MHz in
current case.
This also matches the max clock speed for the m4 core (200MHz)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
cores
In order to prevent potential misconfiguration set the clock setting,
which impacts both cores, under board.defconfig file which is used
by both core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
