STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Write all the desired values in the debug control flag.
Initally we were oring it, but this variable does not have
the expected initial values as it also depends on fuse
programming settings, therefore we dont have console.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Allow the user to use software slave select instead of the
hardware pin, in order to free the related GPIO and avoid
unwanted SS triggering on the hardware pin. The default SS
is still the hardware pin.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Musca B1 has 2 x 2MB embedded flash memories (eFlash). The flash
memories are connected to the AHB Master Expansion “Code Interface”.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This property is only declared in bindings/spi/nordic,nrf-spis.yaml ('s'
for 'slave'), not in bindings/spi/nordic,nrf-spi.yaml.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add the link between the i2c and the arduino connector,
here i2c5.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
I2C5 are used by arduino connector.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
We generated a define for each instance to convey its existance of the
form:
#define DT_<COMPAT>_<INSTANCE> 1
However we renamed all other instance defines to be of the form
DT_INST_<INSTANCE>_<FOO>. To make things consistent we now generate a
define of the form:
#define DT_INST_<INSTANCE>_<COMPAT> 1
We also now deprecate the DT_<COMPAT>_<INSTANCE> form and fixup all uses
to use the new form.
Fixes: #17650
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As we now have PPP support, use more generic "serial-net" string instead
of "slip" when setting what kind of networking the board supports.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Expose eSPI block with interrupts enabled for channel 0 & 1
eSPI handshake has been tested using espi driver sample app
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Particle released documentation with a pre-release flash chip. Correct
the name to the actual as-sold device, and add the corresponding size
property as well as the has-be32k property. Also add an alias so we
can set partitions externally.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The JEDEC API defines the hardware page, sector, and block sizes.
Deprecate the Kconfig settings, remove the `erase-size-block` property,
and add `has-be32k` to indicate that 32K-byte erase is supported.
Rework the driver to use the constants instead of configured values.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The property is required on all SPI clients, but was missing from
several devicetree nodes. Set it, using the capitalized version of the
node alias when present, with "jedec,spi-nor#0" as the fallback.
Closes#17662
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The binding for arm,cmsdk-timer requires a label so add it into the dts
since its missing on v2m_musca_b1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The bindings for arm,cmsdk-{d}timer requires a label so add it into the
dts since its missing on mps2_an521.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
spi-max-frequency is marked as required in
dts/bindings/mtd/jedec,spi-nor.yaml.
I took the value from the datasheets (133 MHz for all), and guessed that
a dummy entry is fine for QEMU.
Fixes some errors in
https://github.com/zephyrproject-rtos/zephyr/issues/17532.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Activate the DTCM for STM32F7 board that have Ethernet.
This is needed because the Ethernet driver puts the DMA buffer
to this section.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
This commit adds a fixed clock node (representing clock driving
system bus). The added node is then referenced by peripherals requiring
information about driving clock frequency.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit adds 'clock-frequency' property to the cpu nodes.
The clock frequency specified in the added property is used
during platform configuration. Examples:
- The SWO logger uses clock frequency to configure SWO output.
- Plenty of platforms need CPU clock specified for their HAL.
- Most of devices with USB needs information about CPU clock
in order to configure USB clock source.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
When TRUSTED_EXECUTION_NONSECUCRE is selected, we always
define the default board (mps2_an521). We do not need to
OR with TRUSTED_EXECUTION_SECURE, in this Kconfig
conditional.
In addition to that, we make the BOARD_MPS2_AN521 board
to strictly depend on the corresponding SOC, not on the
SOC series.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Signify that the MPS2 AN521 is selected as a QEMU
target. Indicate, also, that this board has support
for COVERAGE.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
CONFIG_ARCH_HAS_USERSPACE is automatically set for
Cortex-M targets with CONFIG_ARM_MPU being set. So
we can remove this from the default setup since it
is redundant.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The spi-nor flash nodes require a jedec-id property as per the binding.
We add the jedec-id's as best we can determine based on the data sheets
for the various flash modules on these boards.
However these id's should be validated by actually reading the value to
ensure they are correct.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove whitelisting and enable broader testing on all boards with needed
features.
Add pwm to board yaml where it applies.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
