Commit graph

5973 commits

Author SHA1 Message Date
Kumar Gala
f6b7dd09ec pinmux: sifive: Convert SiFive pinmux to be devicetree based
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:33:00 -05:00
Kumar Gala
4276d7d247 pinmux: hsdk: Convert ARC HSDK pinmux to be devicetree based
Add a simple pinctrl node for the CREG GPIO MUX register to be used
by the pinmux driver.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:29:56 -05:00
Scott Worley
2b926db4e1 drivers: espi: Microchip eSPI add SAF support
Add ESPI SAF features to the Microchip eSPI driver as
a separate file. ESPI SAF depends upon the core eSPI
driver adding the ability to attach the system SPI
flash to the EC eSPI endpoint instead of the host
eSPI controller.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-02-15 08:22:01 -05:00
Daniel Leung
5c649921de x86: add kconfigs and compiler flags for MMX and SSE*
This adds kconfigs and compiler flags to support MMX and SSE*
instructions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-02-15 08:21:15 -05:00
Giancarlo Stasi
dd94c3054b soc: arm: stm32l4: wakeup from stop clock selection based on sysclk
When exiting Stop mode, if system clock is MSI, MSI oscillator is
selected as wakeup from stop clock; otherwise HSI16 oscillator is
selected.

Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
2021-02-15 08:19:27 -05:00
Ryan Holleran
b417bb85d2 dts: nxp_k2x: Correct and enable MCG clock controller binding
nxp_k2x.dtsi: Corrects Multipurpose Clock Generator binding
to utilize nxp,kinetis-mcg. Assign MCG to FlexTimer devices.
Enable FlexTimer clocks via System Integration Module clock
gate control registers.

Kconfig.defconfig.mk22f12: Enable default use of
CLOCK_CONTROL_MCUX_MCG when CLOCK_CONTROL is selected.

Signed-off-by: Ryan Holleran <rhollerar@gmail.com>
2021-02-15 08:14:06 -05:00
Christian Taedcke
9c24fd0a78 soc: silabs_exx32: Always enable SOC_GECKO_CORE
This is required for gecko sdk v3.1.0.

Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
2021-02-15 08:11:52 -05:00
Mulin Chao
ea00ff32fe driver: intc: npcx: remove 'interrupt disable' in miwu configure func.
In this CL, npcx_miwu_interrupt_configure is no longer responsible for
turning the interrupt off. Although the default state of WK_EN is
disabled, the users still have the chance to configure them when WK_EN
is enabled via npcx_miwu_irq_enable(). Hence, this CL also ensures that
WK_EN is disabled before configuring them.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-02-15 08:11:06 -05:00
Flavio Ceolin
86a624e2a2 power: Remove PM_STATE_LOCK option
Simplify pm subsystem removing PM_STATE_LOCK option. Constraints API is
small and is a key component of power subsystem.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-02-15 08:08:36 -05:00
Bernhard Krämer
3ffb223a7f spi: Add LPSPI support for i.MX RT1062 and RT1064
This activates spi support for this soc. Closes #26428

```tests/drivers/spi/spi_loopback``` succeeded.

Signed-off-by: Bernhard Krämer <bdkrae@gmail.com>
2021-02-15 08:06:48 -05:00
Gerard Marull-Paretas
10532a5310 soc: arm: st_stm32: add support for STM32 backup SRAM
Add support for backup SRAM initialization found in multiple STM32
microcontrollers. Linker script facilities are also provided to make it
easy to define variables in the backup SRAM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-02-15 08:04:24 -05:00
Manuel Forcén Muñoz
95c7b58330 dts: arm: st: add support for STM32F205xx SOC
STM32F205xx device tree include files added.
Tested properly in a custom board.

Signed-off-by: Manuel Forcén Muñoz <manuforcen@gmail.com>
2021-02-14 22:10:28 -05:00
Martí Bolívar
60ce0e41fd soc: nrf: fix NRF_DT_CHECK_GPIO_CTLR_IS_SOC
This was merged by mistake without being tested and is not working
properly. We need to avoid doing a BUILD_ASSERT() when the relevant
property is missing, because we can't use DT_GPIO_CTLR() on an
undefined property. Handle this with COND_CODE_1().

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-02-14 16:15:16 -05:00
Andy Ross
746c65acb7 soc/intel_adsp: Move KERNEL_COHERENCE to cavs15
Only the CAVS 1.5 linker script has full support for the coherence
features, don't advertise it on the other SoC's yet.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-02-11 14:47:40 -05:00
Adam Jeliński
86ca5ff562 m2gl025_miv: Adjust frequencies and performance
The default frequency for this board in Renode is 66 MHz. This needs to
be even with `SYS_CLOCK_HW_CYCLES_PER_SEC` to avoid such problems as in
the #31726 issue.

Unfortunately, the difference in these values was helpful for some tests
that are failing with 66 MHz set in both places. It created artificial
boost in certain circumstances.

The frequencies in the default Renode platform description (`.repl`)
file for MI-V were overridden with 4 MHz value that seems to be better
tolerated based on testing. The `SYS_CLOCK_HW_CYCLES_PER_SEC` was
adjusted as well.

To solve the rest of the issues, `cpu PerformanceInMips` was set to 4.
It seems tests are completed faster with such a value.

This commit fixes #31726.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
2021-02-09 19:41:27 -05:00
Detlev Zundel
2155e19414 soc: arm: arm: Align Kconfig input prompt for Arm SoCs
According to https://www.arm.com the correct spelling is now "Arm".
Change the Kconfig input prompts to comply.

Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
2021-02-05 09:48:30 -05:00
Detlev Zundel
daf08da2f3 soc: arm: designstart: Fix Kconfig LEADING_SPACE checkpatch problem
This is a trivial patch replacing the spaces at the beginning of the
line with tabs.  Otherwise checkpatch will not be happy with any
changes in here.

Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
2021-02-05 09:48:30 -05:00
Detlev Zundel
979c748e49 soc: arm: st_stm32f2x: Convert Kconfig input prompt to uppercase
The STM32F2x was the only one of the STM32 series with a lowercase
input prompt.  This looks odd in the SoC selection in 'menuconfig'.

Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
2021-02-05 09:48:30 -05:00
Katsuhiro Suzuki
85315c1238 soc/riscv: support reboot for QEMU RISC-V VirtIO
This patch adds reboot function for QEMU RISC-V VirtIO board.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-02-04 13:14:12 -05:00
Erwan Gouriou
9abff32bdc drivers/watchdog: stm32: Select watchdog using compatible
Rather than Kconfig vendor symbols, select stm32 watchdog using
compatible.
So user only has to enable the requested node and set
CONFIG_WATCHDOG=y.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-02-02 08:15:51 -05:00
Giancarlo Stasi
5b025d0d9b soc: arm: stm32l4: Fix stm32 ll header list
PM stm32 ll header list was not adequate for L4 debug builds.
Add _system.

Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
2021-02-02 07:18:16 -05:00
Mulin Chao
ddd73ca508 driver: espi: add more KBC 8042 support in npcx series.
This CL added more additional details for KBC (Keyboard and Mouse
Controller) bus in espi_event structure. It helps the application to
handle different 8042 events in the callback function.

The format of event data for KBC 8042 protocol is:
[23:16] - 8042 event type: 1: Input buf full, 2: Output buf empty.
[15:8]  - 8042 data: 8-bit 8042 data.
[0:7]   - 8042 protocol type: 0: data type, 1: command type.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-02-01 21:42:44 -05:00
Peter Bigot
e9b5be36db soc: nordic: disable system power management on nRF53 network core
The network core doesn't have access to the regulators necessary to
support system power management.  That has to be done on the
application core.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-02-01 15:05:03 -05:00
Peter Bigot
5d2acb30eb Revert "soc: nordic: Disable PM for SOC_NRF5340_CPUNET_QKAA"
This reverts commit f38ba314ea.

nrf5340dk_nrf5340_cpunet doesn't support power management, but that
should be handled another way.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-02-01 15:05:03 -05:00
Vincent Wan
66ed8d53e5 soc: cc13x2_cc26x2: add support for soft off power state
The soft off power state should be supported as it is closest to what
used to be deep sleep state 1, which corresponds to the device off
state supported by hardware.

Fixes #31727.

Signed-off-by: Vincent Wan <vanti.coder@gmail.com>
2021-01-28 08:15:55 -05:00
Scott Worley
af67564573 soc: mchp: Update 32KHz programming sequence
Based upon discussions with HW designers the 32KHz
    programming sequence can be simplified. When FW writes
    a value to the VBAT 32KHz Clock Enable register HW checks
    if the value is the same as the current value. If the same
    the HW does nothing. If different HW begins a sequence to
    switch off the current 32KHz source, revert to ring oscillator,
    and switch to the new source. FW should program the new value
    and then spin until the PCR OSC ID PLL Lock bit goes to 1.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-01-27 21:37:39 -05:00
Eugeniy Paltsev
065dc42516 ARC: soc: hsdk: add MWDT compiler options
HSDK board misses MWDT compiler options, so CCAC uses default
ones (which doesn't match HSDK HW) when building with MWDT.

Add MWDT compiler options.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2021-01-26 06:18:02 -05:00
Volodymyr Babchuk
b07065d3f3 arm: aarch64: add Xen virtual machine support
This commit adds minimal support for running zephyr as Xen guest. It
does not use xen PV console, which is somewhat hard to implement, as it
depends on xenbus infrastructure. Instead SBSA-compatible PL011 uart is
used.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
2021-01-24 13:59:55 -05:00
Andrew Boie
f3e9b61a91 x86: reserve the first megabyte
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-23 19:47:23 -05:00
Shubham Kulkarni
9f139b5d83 soc/esp32: Move full logging library to IRAM
This commit updates linker script to move full logging module into
internal RAM

Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
2021-01-23 08:43:10 -05:00
Shubham Kulkarni
d621dad21b soc/esp32: Move logging library to IRAM with CONFIG_LOG_MINIMAL
This commit updates linker script to move minimal log module to internal
RAM

Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
2021-01-23 08:43:10 -05:00
Shubham Kulkarni
ca39c7edd7 soc: esp32: linker: Fix backtrace for Invalid cache access exception
This change moves .rodata for panic handler and fatal.c into DRAM
Moves panic handler and its dependent functions into IRAM

Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
2021-01-23 08:43:10 -05:00
Andrei Gansari
6d86a6a139 soc: lpc54xxx: add memory controller definitions
Adds device tree and kconfig definitons to use legacy LPC IAP flash
driver.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2021-01-23 08:01:00 -05:00
Alexey Brodkin
7e8fa999bf ARC: QEMU: Enable icount support
This allows to get much more reproducible results in terms of
amount of tests passed & failed.

But note it requires QEMU for ARC with icount support!

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2021-01-23 00:42:13 -05:00
Maureen Helm
c489cf99e2 soc: arm: Enable FlexSPI flash driver on i.MX RT family
Enables the FlexSPI flash driver on the i.MX RT SoC family and
configures the peripheral clocks accordingly. We are careful to only
configure the peripheral clocks if we are not executing in place from
the FlexSPI flash.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-01-22 11:11:54 -05:00
Maureen Helm
1883c85abd modules: nxp_imx: Add HAS_MCUX_FLEXSPI
Adds a hidden config symbol HAS_MCUX_FLEXSPI selected by NXP SoCs when
the FlexSPI peripheral is present. It will be used as a dependency for a
new FlexSPI flash driver to prevent users from accidentally enabling the
driver on platforms that don't have the necessary hardware.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-01-22 11:11:54 -05:00
Flavio Ceolin
f38ba314ea soc: nordic: Disable PM for SOC_NRF5340_CPUNET_QKAA
This targets was previously enabling PM but the code was doing nothing
because the logic was under an unsatisfied ifdef condition.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-22 09:31:20 -05:00
Flavio Ceolin
7f48e992e8 soc: efm32wg: Select SOC_GECKO_CORE if pm is enabled
Power management requires core interrupt handling.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-22 09:31:20 -05:00
Flavio Ceolin
321ce7fb77 power: Use substate-id in pm subsystem
Change subsystem to use struct pm_state with substate-id instead of
using only the power state category.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-22 09:31:20 -05:00
Flavio Ceolin
d21808b0b1 power: Remove residency and states from Kconfig
Residency time and power states are defined using device tree now.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-22 09:31:20 -05:00
Flavio Ceolin
d21cfd5f36 power: Remove power management conditionals from code
Remove conditionals (PM_DEEP_SLEEP_STATES and PM_SLEEP_STATES) from
power management code. Now these features are always available when
power management is enabled.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-22 09:31:20 -05:00
Flavio Ceolin
579f7049c7 power: Move pm subsystem to new power states
Migrate the whole pm subsystem to use new power states information
from power_state.h and get states and residency properties from
device tree.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-01-22 09:31:20 -05:00
Anas Nashif
4422b1d376 Revert "x86: reserve the first megabyte"
This reverts commit 51e3c9efa5.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-22 08:39:45 -05:00
Andrew Boie
51e3c9efa5 x86: reserve the first megabyte
A more comprehensive solution would use E820 enumeration, but we
are unlikely to ever care that much, as we intend to use demand
paging on microcontrollers and not PC-like hardware. This is
really to just prevent QEMU from crashing.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2021-01-21 16:47:00 -05:00
Lucien Zhao
fe0e01d83f soc: arm: nxp_imx: rt: mimxrt1024: add device support
- Add soc information for RT1024

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2021-01-21 14:50:45 -05:00
Enjia Mai
dd792ee11b tests: common: fix kernel.common test case build fail in intel_adsp_cavs
Fix kernel.common and kernel.common test cases fail due to build error
in platform intel_adsp_cavs15, 18, 20, 25.

Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
2021-01-21 14:47:31 -05:00
Gerson Fernando Budke
f93ee9508b soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support
PSoC-6 SoC needs that user define the nvic interrupt number to bind
with the peripheral interrupt line for the Cortex-M0+ CPU.  It uses
a multiplex before any NVIC interrupt line.  The interrupt vector is
selected using interrupt-parent property with the intmux_chN number
reference.

Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt.
A tipical use is GPIO interrupt handle and user is responsable to
define interrupt line, priority and take care of enable same peripheral
instance on both CPUs only when appropriated.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-20 17:54:09 -06:00
Gerson Fernando Budke
2ad591f756 soc: arm: cypress: psoc6: Update soc.h includes
Update <soc.h> include files.  This removes the unnecessary
<kernel_includes.h> file.  In addition, add <sys/util.h> to
expose macros and <devicetree.h> following general standards.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-01-20 17:54:09 -06:00
Henrik Brix Andersen
8167134f05 drivers: pwm: add driver for the NXP Kinetis Pulse Width Timer (PWT)
Add PWM capture driver for the NXP Kinetis Pulse Width Timer (PWT).

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-01-20 08:05:57 -06:00
Johan Hedberg
05f8dd9ab9 drivers: i2c_dw: Remove hard-coded instance count assumption
Introduce a Kconfig variable that the SoC can set to indicate the
number of instances in Device Tree. This also fixes the accuracy of
the Elkhart Lake instance count where the code was previously assuming
up to 12 instances even though DT lists 15 nodes.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-19 14:52:29 -05:00