Commit graph

5973 commits

Author SHA1 Message Date
Tim Lin
8a779fc706 ITE: drivers/i2c/target: Introduce I2C target transfer using PIO mode
Introduce I2C target transfer using the PIO mode. Add an option
"target-pio-mode" in the yaml file, determined by the DTS, to dictate
whether I2C target transfer uses the PIO mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-09-07 09:43:06 +02:00
Tim Lin
3ae9a358fb ITE: drivers/i2c/target: Disable the timeout setting
Disable the timeout setting when both the clock and data are
in a low state. This allows for I2C host clock stretching
without a timeout limit.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-09-07 09:43:06 +02:00
Richard Wheatley
a92008c17d soc: arm: ambiq: apollo4: add simobuck init to apollo4 init
Adds comments and simobuck init function for low power.

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2023-09-06 09:33:06 +02:00
Warren Buffer
09577b0a0e soc: Added support for EFR32MG12P433F1024GM68
Added devicetree and Kconfig for EFR32MG12P433F1024GM68, needed for
the BRD4170A radio board by Silicon Labs.

Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
2023-09-05 16:16:30 +02:00
Gerard Marull-Paretas
35479cccac soc: arm: atmel_sam0: common: bossa: add missing init.h
Because modules uses SYS_INIT, from init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-05 12:19:04 +02:00
Vinayak Kariappa Chettimada
9ede8cd87e dts: nRF: Add missing headermask binding for NRF_CCM
Add missing headermask binding for NRF_CCM peripheral and
define HAS_HW_NRF_CCM_HEADERMASK Kconfig.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2023-09-05 10:04:57 +02:00
Adrian Warecki
b26921d776 dai: intel: dmic: New functions for writing fir coefficients
Created set of new functions for configure fir coefficients with support
for packed format. This allowed to make the dai_dmic_set_config_nhlt
function simpler.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-09-04 15:30:00 -04:00
Adrian Warecki
2452aaad50 dai: intel: dmic: Separate fir configuration code into function
All fir filters have an identical set of registers so their definitions
were combined to simplify the code. From the dai_dmic_set_config_nhlt
function, a duplicate piece of code responsible for configuring fir was
separated into a new function.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-09-04 15:30:00 -04:00
Adrian Warecki
d7672af838 dai: intel: dmic: Combine PDM registers definitions
All PDM controllers have the same set of registers. Their definitions have
been merged to simplify the code.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-09-04 15:30:00 -04:00
Alberto Escolar Piedras
d9c76e6fe1 native SOC: Add option to select CPU we target
Add a new kconfig option to select which embedded
CPU we are targetting.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-09-04 13:18:01 +02:00
Gerard Marull-Paretas
4747218837 soc: arm: ti_simplelink: cc13x2_cc26x2: compile power.c if PM_DEVICE=y
power.c contains some struct definitions required by the HAL when using
PM_DEVICE.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-04 12:22:55 +02:00
Sreeram Tatapudi
09a07e42c0 drivers: cat1: Updates to support latest version of HAL/PDL
- Refactoring to support latest versions of HAL/PDL

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2023-09-01 09:52:25 +02:00
Kai Vehmanen
5689916a70 soc: xtensa: intel_adsp: cavs: fix assert on L3_MEM_BASE_ADDR
The assert on L3_MEM_BASE_ADDR is incorrect, we need must convert
to uncached before use.

Fixes: ffd2121c65 ("soc: xtensa: intel_adsp: cavs: fix
  power_down_cavs() signature")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-08-31 17:43:47 -04:00
Adrian Bonislawski
a026370461 drivers: hda: use interrupt for timing L1 exit on host DMA
To properly setup L1 exit timing this patch will use buffer interrupt
for HOST DMA and wait for Host HDA to actually start
First interrupt will clear all others.

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-08-31 09:59:10 -04:00
Adrian Bonislawski
b7e181c270 soc: intel_adsp: add HDA buffer interrupt functions
This will add functions to configure HDA buffer interrupts

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-08-31 09:59:10 -04:00
Adrian Bonislawski
c6c6c5a5ed soc: intel_adsp: ace shim: add force L1 defines
This will add force L1 defines for svcfg registry

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-08-31 09:59:10 -04:00
Gerard Marull-Paretas
c315c9b97c soc: arm: ti_simplelink: cc13x2_cc26x2: add support for sys_poweroff
Implement sys_poweroff() hooks, based on previous SOFT_OFF
implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 14:42:26 +02:00
Almir Okato
af3b04238e soc: espressif: adjust memory organization on linker
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Almir Okato
e946a13fe1 soc: espressif: fix SOC series name macro on loader.c
Update macro CONFIG_SOC to CONFIG_SOC_SERIES.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Rahul Arasikere
da55c26593 soc: arm: Add Kconfig option for SOC_STM32F765XX
Adds a new Kconfig menuchoice for the STM32F765xx series.

Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
2023-08-31 10:21:25 +02:00
Dino Li
003e0be6fb it8xxx2/linker: append h2ram_pool section at the end of used memory
Since __sha256_ram_block section must in the first 4KB,
h2ram_pool section is no longer included first inside the
RAMABLE_REGION.
Append h2ram_pool section at the end of used memory, so gap
due to alignment is still available for newly added variables.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2023-08-31 10:20:17 +02:00
Gerard Marull-Paretas
b459064ec1 soc: arm: st_stm32: wl: add support for sys_poweroff
Implement the hook for sys_poweroff based on the SOFT_OFF code. Note
that standby mode was a substate of SOFT_OFF, however, it was not
supported judging from defined DT states. It can be added later using
the STANDBY state.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
574360cba0 soc: arm: st_stm32: wba: remove redundant entry in pm_exit_post_ops
SOFT_OFF is not supported for this SoC, also, SOFT_OFF will never reach
the PM post ops.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
d7a0b4fa93 soc: arm: st_stm32: u5: add support for sys_poweroff
Add support for the sys_poweroff hook, re-using code from the SOFT_OFF
state.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
b97b17a4f5 soc: arm: st_stm32: wb: add support for sys_poweroff
Implement the sys_poweroff() hook. The hsem locking is not part of the
implementation, it doesn't seem necessary after
https://github.com/zephyrproject-rtos/zephyr/pull/42409 but I may be
wrong. Needs verification.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
643383b060 soc: arm: st_stm32: l4: add support for sys_poweroff
Convert SOFT_OFF handler to sys_poweroff hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
11242691cd soc: arm: st_stm32: l0: remove unsupported state
SOFT_OFF state (which translates to standby) doesn't seem to be
supported according to the L0 DT files. Also, by definition soft off
implies context loss, ie boot from scratch, but the implementation
expected a call to the PM exit hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
cd97eae73b soc: xtensa: intel_adsp: common: s/device.h/init.h
soc.c was not using any device.h API, but init.h (SYS_INIT).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 14:43:01 +02:00
Gerard Marull-Paretas
6cdabb4dff soc: xtensa: intel_adsp: common: add missing section_tags.h
Needed by the `__imr` section tag.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 14:43:01 +02:00
Gerard Marull-Paretas
c360284c6e soc: xtensa: intel_adsp: add missing init.h
Some files were using SYS_INIT without including init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 14:43:01 +02:00
Gerard Marull-Paretas
00ff421129 soc: arm: nxp_imx: rt10xx: s/device.h/init.h
File was not using any device.h API, but init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:50 +02:00
Gerard Marull-Paretas
b3b8a19e02 soc: arm: nuvoton_npcx: common: s/device.h/init.h
File was not using any device.h API, but init.h (SYS_INIT).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:35 +02:00
Gerard Marull-Paretas
47fba91367 soc: riscv: telink_b91: add missing init.h, devicetree.h
File was including device.h for nothing, it needs init.h and
devicetree.h instead.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:51:57 +02:00
Kai Vehmanen
ffd2121c65 soc: xtensa: intel_adsp: cavs: fix power_down_cavs() signature
The second argument 'uint32_t *hpsram_pg_mask' must be a cached
pointer and this needs to be reflected in function prototype.

Fixes sparse warning:
/zep_workspace/zephyr/soc/xtensa/intel_adsp/cavs/power.c:106:63:
warning: incorrect type in argument 2 (different address spaces)

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-08-30 10:22:45 +02:00
Kai Vehmanen
a1d7ffdc37 soc: xtensa: intel_adsp: cavs: fix incorrect cached/uncached cast
Converting between cached and uncached aliases should have correct
sparse annotations. Fix following sparse warning:

/zep_workspace/zephyr/soc/xtensa/intel_adsp/cavs/power.c:97:53: warning:
incorrect type in argument 1 (different address spaces)

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-08-30 10:22:45 +02:00
Tristen Pierson
1f2180e8ff drivers: adc: adc_sam0: fix c20 and c21 reference not setting
drivers: adc: adc_sam0: fix c20 and c21 reference not setting

On c20 and c21 variants, the adc_sam0 driver is failing to honor the
enable-protected status of the REFCTRL register when writing the channel
config's reference into it. This causes the reference to never be set
when adc_sam0_channel_setup is called since the ADC is not disabled
prior to the write. Fix it by adding the
ADC_SAM0_REFERENCE_ENABLE_PROTECTED definition to the c20 and c21 soc.h
files. This effectively disables the ADC during writes to the REFCTRL
register, thus honoring the enable-protected behavior of this register.
I'm assuming ADC_SAM0_REFERENCE_ENABLE_PROTECTED exists for this type
of situation and therefore this was the approach taken. After making
the change, I was able to verify proper ADC readings by measuring
voltage on an ADC pin and observing correct values. Reverting back prior
to this change, running the same test yields reading 0's.

Fixes: #61975

Signed-off-by: Tristen Pierson <tpierson@bitconcepts.tech>
2023-08-30 10:21:15 +02:00
Francois Ramu
66caf58265 soc: arm: stm32h7x mapping system memory region
System memory declared by the MPU as 'Strongly Ordered'
with region attributes which will inhibit the speculative fetch,
preventing the Flash RDSERR.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-08-30 10:17:39 +02:00
Kai Vehmanen
ce7c30c129 soc: intel_adsp/ace: use WAIT_FOR for core power transitions
Use WAIT_FOR to wait for core power changes to be reflected
in status registers. If core power state does not complete in
10ms, k_panic() is raised.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-08-29 16:14:18 +02:00
Gerard Marull-Paretas
f88d21cdb9 soc: arm: nordic_nrf: nrf53: sync_rtc: add missing init.h
File was using SYS_INIT, from init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-29 14:35:45 +01:00
Kai Vehmanen
c6284d4afe soc: adsp: clk: use WAIT_FOR() to wait on clk power-up
Use WAIT_FOR to wait for clock source to be enabled. If clock does
not come up in 10ms, raise k_panic().

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-08-29 06:54:02 -04:00
Anisetti Avinash Krishna
0f796a4b2a soc: x86: alder_lake: soc_gpio: Modified instance count
Updated GPIO instance count of ADL

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-08-29 10:24:03 +02:00
Mulin Chao
f942b44c56 soc: arm: npcx: move workaround methods for npcx series to its soc.c
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-28 08:22:10 +01:00
Daniel Leung
169f505226 xtensa: add support for dc233c SoC for QEMU
This adds SoC and board configs to support the dc233c core
that is available on QEMU. This core has more features than
sample_controller, such as MMU support.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-08-26 16:50:40 -04:00
Maximilian Deubel
4cde3ea70f soc: arm: nordic_nrf: nrf91: rename nRF9161 SICA to LACA
This patch corrects the name of the nRF9161,
which is LACA, not SICA.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 13:48:17 +02:00
Maximilian Deubel
dc954977b7 soc: arm: nordic_nrf: nrf91: add nRF9131 LACA
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 11:56:12 +02:00
Mateusz Sierszulski
be149593c9 drivers: pinctrl: Add more config options for Ambiq Apollo4
This commits add more configuration options
for Ambiq Apollo4 pinctrl driver.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2023-08-25 10:31:58 +02:00
Tim Lin
ed37374dac ITE: drivers/pwm: Add the flag of PWM output open-drain mode
This flag is used when the PWM output is set to open-drain mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-08-25 10:31:42 +02:00
Marcin Niestroj
19d7b26238 soc: arm: stm32h5: support SWO
In case of stm32h5 both LL_DBGMCU_EnableTraceClock() and
LL_DBGMCU_SetTracePinAssignment() need to be called in order to properly
configure SWO output.

Select HAS_SWO, so that logging over SWO can be enabled.

Tested with ST's fork of openocd [1].

[1] https://github.com/STMicroelectronics/OpenOCD

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2023-08-24 18:21:52 -05:00
Daniel DeGrasse
905512438e soc: arm: nxp_imx: update iMX RT boot header to handle CONFIG_XIP=n
Update iMX RT boot header to support CONFIG_XIP=n, when the image is not
linked into the flash space. Also, update the boot header to correctly
calculate the flash used size within the boot data header. This field is
used by the iMX boot ROM to determine how much data to copy when running
from RAM, so using the correct size fixes an issue where the ROM would
copy more data than needed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-24 22:09:01 +01:00
Gerard Marull-Paretas
94a4d38ed9 cmsis: remove unnecessary includes
Some files included <cmsis_core.h> for nothing, delete it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00