Many xtensa target jump from soc code directly into cstart and depend on
architecture code being initialized in arch_kernel_init(). Instead of
jumping to cstart, jump to newly introduced prep_c similar to all other
architectures, where common platfotm initialization will happen.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
cplusplus-rom linker initialization was wrongly placed
in RAM area when it should be in ROM area.
Fixes#75853
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
In addition to Kconfig options (soon to be deprecated), allow
configuring the regulators using DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Previously, the `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 did not register the log module. This caused build
errors when DEBUG logging was enabled, as the `power.c` file attempted
to access a non-existent SOC log module for debug messages.
This commit fixes the issue by registering the log module in the
`soc.c` files for the specified SoCs, thereby resolving the build
errors.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Fix formatting for `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 by running 'clang-format'.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Convert NXP System Timer Module driver to a native driver.
Timer prescaler in tests is updated because short relative alarms
sometimes give false positives.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow developer to use the baremetal Bluetooth functionalities of the
CC13X2 and CC26X2 series SoCs without having to use the full Zephyr
Bluetooth stack.
Signed-off-by: Benedikt Streicher <streicher.b@posteo.de>
Convert NXP SWT watchdog driver to a native driver and extend the
SWT supported functionalities and configuration options.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert power management to native drivers retaining existing
functionalities. Presently only SoC reset support and power control
initialization is supported, but these drivers will be extended to
support power management as well.
MC_ME and MC_RGM peripherals are common enough to be reused by other NXP
S32 devices, whereas PMC has specific implementations for each SoC
series.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow CONFIG_NRF_APPROTECT_LOCK and
CONFIG_NRF_SECURE_APPROTECT_LOCK with TF-M with all the SOC's
that support TF-M.
Signed-off-by: Markus Lassila <markus.lassila@nordicsemi.no>
Split SIUL2 instance index for the MSCR and IMCR registers as required
by some pins. Pinmux macros definitions in hal_nxp must be updated
accordingly.
Fixes#76147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It seems this SiP variant is not sold by espressif directly, but it is
used by the Odroid Go. The Odroid Go documentation calls this a "custom"
model [1].
There already exists a SiP specific device tree include file:
zephyr/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi
[1] https://wiki.odroid.com/odroid_go/odroid_go#specifications
Signed-off-by: Gero Schwäricke <gero.schwaericke@posteo.de>
DMM shall be initialized as early as possible to allow drivers to
use it. For example, uart may need it early since it starts
RX during initilization in some configurations.
Making dmm_init() public and calling it in soc init function.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support of sys_poweroff API on m46x series.
It could support SPD standby or DPD deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Remove the ‘HAS_MCUX_ACMP’ Kconfig, and also remove it from
driver and soc Kconfig files. It is not needed since we already
depend on 'ACMP' enabled in the dt file, the 'HAS_MCUX_ACMP'
kconfig is a relic of the past before devicetree was stable.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
When not using BT, users may want to enable the cpunet core. Until now,
this has been done at board level (so duplicating unnecessary code)
using CONFIG_BOARD_ENABLE_CPUNET. The board-level options were usually
enabled automatically for BT, however, this was unnecessary as BT driver
already takes care of the setup.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The total number of IRQs for this chip is 110.
Refer to the reference manual table 46 for IRQs.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
Place zephyr library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libzephyr.a: +16974 bytes -608ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place kernel library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libkernel.a: +8941 bytes -649ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place serial library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libdrivers__serial.a: +2282 bytes -226ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Initialize TCM and SRAM contents only after a destructive reset (e.g.
PoR reset). SRAM retains content during functional reset through a
hardware mechanism, therefore accesses do not cause content
corruption errors.
Fixes#75912
Signed-off-by: Manuel Argüelles <marguelles.dev@gmail.com>
In S32K1 devices, Arm Systick clock frequency is equal to the
CPU core clock frequency, and its value can be obtained from
devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Currently the code suggests, that setting the SRAM disabling mask to
0 skips powering off SRAM, whereas in fact it's the address of the
mask variable that's checked for NULL. Make this consistent and let
platforms select whether SRAM power down should be selected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The IMR is used by the firmware to hold its own copy for hot-booting
and for an "L3 heap," used for slow large allocations like loadable
libraries. The beginning of the L3 heap is currently hard-coded and
now the firmware has grown too large to fit into the dedicated area
so that it gets overwritten by heap allocations. This is a critical
bug that needs an urgent solution, for which we increase the offset,
but a real fix must calculate the L3 heap offset automatically.
BugLink: https://github.com/thesofproject/sof/issues/9308
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
After recent nsim SoCs & boards reorganization the SOC_SERIES_*
config is missing for vpx5 SoC which leads to cmake errors
when building against nsim/nsim_vpx5 configuration.
Fix that and align soc series name in soc.yml
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The source files required for this features are not present
in the tree for this SOC.
So if CONFIG_PM or CONFIG_POWEROFF are enabled, there would
be a cmake failure.
Let's just indicate these features are not supported in
kconfig.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
CLIC should be the first level interrupt controller because it replaces
the basic RISC-V local interrupt.
The interrupt level in CLIC controls preemption between IRQs, rather than
specifying the number of nested interrupt controllers.
Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
A recent commit fb53d2ef8d ("ace: power: replace pseudo-assembly
movi") contained a bug: the Xtensa "movi" assembly instruction must
be written with the immediate argument already shifted left by 8, the
compiler doesn't do that automatically. This still somehow worked on
MTL but failed on LNL. Fix both occurrences.
Fixes: #75700
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
SARADC was kept enabled to feed RNG entropy peripheral,
adding instability to Wi-Fi connection. So we disable it
before app runs as RNG driver already got initial entropy values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Getting the required alignment size for memory region node
and device node needs to be handled by a separate macro.
Otherwise alignment of single byte is reported for any region.
Add a test that checks for this particular issue.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The series-specific Kconfig files were not included, leading
to RTT not being considered available.
Fixes#75511.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
