Commit graph

503 commits

Author SHA1 Message Date
Gerard Marull-Paretas
7da6342dff soc: riscv: virt: reorganize SoC folder
Move out of riscv-privileged, and convert to single SoC (no
family/series).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
b7b19b8b05 soc: riscv: neorv32: reorganize SoC folder
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
7a44806a53 soc: riscv: s/litex-vexriscv/litex_vexriscv
To be consistent with other SoCs in the same folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
4a0d880350 soc: riscv: ite: reorganize SoC folder
Follow the vendor structure [1]:

- Family: ITE Embedded Controller SoCs
- Series: IT8XXX2
- SoCs: IT81202BX, IT81202CX, etc.

[1]: https://www.ite.com.tw/en/product/category?cid=1

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
8027689392 soc: riscv: andes_v5: reorganize SoC folder
Split out from riscv-privileged folder, and create a new family.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
87f3b07292 soc: riscv: starfive_jh71xx: reorganize SoC folder
Move it out from RISC-V privileged folder, and create a standalone
family.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
5a98d87335 soc: riscv: gd32vf103: reorganize SoC folder
Move things out from riscv-privileged, and create the new RISC-V GD32
family. New family folder follows the <vnd>_<family> naming convention.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
72e52a06aa soc: riscv: telink_b91: reorganize SoC folder
Reorganize following the hierarchy found in the vendor website [1]:

- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518

Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].

[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
     B91_Generic_Starter_Kit_Hardware_Guide/

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
d8c0cc2e35 soc: riscv: introduce temporary RISCV_PRIVILEGED_STANDALONE
So that SoCs can be ported outside of riscv-privileged folder, setting
their own family name. This will be removed once all SoCs are ported.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
0106e8d14c arch: riscv: introduce RISCV_PRIVILEGED
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.

Note that the SoC family naming scheme will be fixed in upcoming
commits.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
9a35ad858c soc: riscv: gd32vf103: move nuclei CSR header
The header is common to all Nuclei based cores (not strictly related to
RISCV privileged spec). Since only GD32VF103 uses a Nuclei core, move
the file to its SoC folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
6443c50bd0 soc: riscv: move privileged code to common folder
Add a new riscv/common directory where to store common code between
SoCs, e.g. those implementing the privileged spec.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Sylvio Alves
b19c164e7b soc: espressif: add common linker tls entry
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-01-08 15:09:48 +01:00
Yong Cong Sin
c328a38a94 soc: riscv: add support for Renode Virt RISCV32 SoC
Add a beef-ed up version of Renode's `riscv_virt` SoC

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-08 12:35:10 +01:00
Ren Chen
5762d022dc drivers: usb: usb_dc_it82xx2: optimize the basic/extend endpoints control
This commit refactors the basic and extended endpoint control functions to
enhance readability.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2023-12-20 11:15:38 +01:00
Ren Chen
e23ae3b678 drivers: usb: usb_dc_it82xx2: refactor usb driver with macros
Refactor the code using macros to enhance readability.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2023-12-20 11:15:38 +01:00
Conor Paxton
dc5cf9cb1c soc: mpfs: describe the correct amount of irqs available.
Microchip's PolarFire SoC (MPFS) has 186 available interrupts.
Fix the Kconfig symbols.

While we're at at: remove commented out code

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
2023-12-06 17:54:29 +00:00
Chen Xingyu
3f7e73416d soc: riscv: privileged: efinix-sapphire: Enable CONFIG_RISCV_HAS_CPU_IDLE
In an earlier commit, the riscv-privileged level implementation of
`arch_cpu_idle()` is not included unless `CONFIG_RISCV_HAS_CPU_IDLE` is
enabled.

This commit ensures the option is enabled on all the existing CPUs, thereby
maintaining the existing behavior.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
2023-11-28 15:34:06 +01:00
Chen Xingyu
34d2c4d6b2 soc: riscv: privileged: Conditionally override arch_cpu_idle()
The current configuration comes with a common implementation of
`arch_cpu_idle()` for the whole riscv-privileged family, utilizing the
`WFI` instruction to place the CPU into a light sleep state, with the
assumption that it will be awakened later by interrupts such as SYSTICK.
However, this approach is not always effective, particularly in scenarios
where the SYSTICK is not a valid wake source.

This commit uses `CONFIG_RISCV_HAS_CPU_IDLE` as the build condition of the
family-level `idle.c`, allowing CPUs that do not enable this option to
fallback to a generic arch-level implementation in
`arch/riscv/core/cpu_idle.c`.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
2023-11-28 15:34:06 +01:00
Sylvio Alves
ca346ba216 soc: esp32: call reset cause reason init
Reset cause reason was not initalized properly, making
hwinfo feature not to work as expected.

Fixes #65634

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-11-27 19:59:45 +01:00
Yong Cong Sin
e538b0e5a6 drivers: plic: support multiple instances for multi-level
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 18:20:43 +01:00
Tim Lin
f1dc11174c ITE: drivers/i2c: Add a property for I2C located channel
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-11-08 10:08:28 +01:00
Torsten Rasmussen
10fea41f5c cmake: riscv: update riscv SoC to use SOC_LINKER_SCRIPT variable
This commit updates all riscv SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-03 11:01:23 +01:00
Ederson de Souza
928e22c302 soc/riscv/riscv-ite/it8xxx2: Support DEVNULL_REGION
it8xxx2 uses a custom linker script, which was not updated on
dfb3674c4c. This patch naively updates it
to support DEVNULL_REGION.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-11-01 18:48:24 -04:00
Yong Cong Sin
d7302f417e irq: relocate multi-level irq out of irq.h
Relocate multi-level interrupts APIs out of `irq.h` into
a new file named `irq_multilevel.h` to provide cleaner
separation between typical irq & multilevel ones.

Added preprocessor versions of `irq_to_level_x` as `IRQ_TO_Lx`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-30 11:43:39 -04:00
Michael Arnold
973e226bfd arch: Enable ramfunc feature on RISC-V PRIVILEGE SOC family
Allow to place functions in ram.

Signed-off-by: Michael Arnold <marnold@baumer.com>
2023-10-25 17:35:07 +02:00
Sylvio Alves
3f5ea785f2 linker: esp32: fix linker to enable proper MMU usage
ESP32 flash_mmap() function requires `_rodata_reserved_start` address
to be at the beginning of RODATA. This allows adding memory-mapped flash
areas.

Fixes #52764

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-10-25 09:57:48 +02:00
Tim Lin
35e3dfed2d ITE: soc: Add the variant of it82002aw
This variant uses the same die as IT82202/IT82302 series and has
a pinout compatible with IT513xx series packages.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-10-20 15:07:28 +02:00
Sylvio Alves
4b5331ba45 linker: esp32: move snippets-section within rom boundary
This will guarantee that application snippets will be placed
into ROM section properly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-10-13 13:10:22 +03:00
Detlev Zundel
42ea06cf21 soc: xtensa,riscv: esp32c3: Fix SOC_PART_NUMBER choices
Add the ESP32-C3-WROOM-02 modules with 4 or 8 MiB flash. The
temperature and antenna / connector variants are not mentioned
explicitely as they do not influence the software.

Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
2023-10-06 12:24:49 +01:00
Yong Cong Sin
93cbfcfee9 board: riscv: qemu: increase ndev of PLIC to 1024
Increase the `ndev` of PLIC to the max of 1024 from 53, as
supported by the RISCV PLIC. The total number of IRQs is now
1035(1024 + 11), up from 64(53 + 11).

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-05 06:10:06 -04:00
Yong Cong Sin
5b9f82668b riscv: telink_b91: fix compilation
Fix compilation failure due to multilevel interrupt.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-18 13:03:45 -04:00
Sylvio Alves
f5fa4b3bcd soc: espressif: provide VMA to rodata and text by default
Flash segments require VMA to proper work. Executing from LMA
is not possible. Current implementation did not take into account
runtime iterable rom sections that any application could implement.
In the above cenario and as reported in the issue below, ESP32 won't run
when those ROM sections are created in application level.

This change make sure all flash segments are properly mapped
accordingly.

Fixes #61834

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-09-18 10:38:03 +01:00
Gerard Marull-Paretas
aaeb0a672e toolchain: only include <zephyr/toolchain.h>
It is wrong to use toolchain-specific header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Huifeng Zhang
2c22e83dfb include: arch: arm: Remove aarch32 directory
This commit follows the parent commit work.

This commit introduces the following major changes.

  1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
    to the 'include/zephyr/arch/arm' directory.

  2. Change the path string which is influenced by the changement 1.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-09-13 10:08:05 +01:00
Tim Lin
8a779fc706 ITE: drivers/i2c/target: Introduce I2C target transfer using PIO mode
Introduce I2C target transfer using the PIO mode. Add an option
"target-pio-mode" in the yaml file, determined by the DTS, to dictate
whether I2C target transfer uses the PIO mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-09-07 09:43:06 +02:00
Tim Lin
3ae9a358fb ITE: drivers/i2c/target: Disable the timeout setting
Disable the timeout setting when both the clock and data are
in a low state. This allows for I2C host clock stretching
without a timeout limit.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-09-07 09:43:06 +02:00
Almir Okato
af3b04238e soc: espressif: adjust memory organization on linker
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Dino Li
003e0be6fb it8xxx2/linker: append h2ram_pool section at the end of used memory
Since __sha256_ram_block section must in the first 4KB,
h2ram_pool section is no longer included first inside the
RAMABLE_REGION.
Append h2ram_pool section at the end of used memory, so gap
due to alignment is still available for newly added variables.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2023-08-31 10:20:17 +02:00
Gerard Marull-Paretas
47fba91367 soc: riscv: telink_b91: add missing init.h, devicetree.h
File was including device.h for nothing, it needs init.h and
devicetree.h instead.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:51:57 +02:00
Tim Lin
ed37374dac ITE: drivers/pwm: Add the flag of PWM output open-drain mode
This flag is used when the PWM output is set to open-drain mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-08-25 10:31:42 +02:00
Gerard Marull-Paretas
3118a8c05c soc: riscv|xtensa: esp32: add support for sys_poweroff
Implement the sys_poweroff hook for all ESP32 SoCs based on the previous
SOFT_OFF implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-15 10:15:38 -07:00
Yong Cong Sin
84b86d9b0c soc: riscv: Add ability to use custom sys_io functions
Add Kconfig RISCV_SOC_HAS_CUSTOM_SYS_IO symbol so that a riscv
SoC can set to specify that it has a custom implementation for
sys_io functions.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-07-26 09:43:59 +02:00
Marek Matej
6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
Gerard Marull-Paretas
55f5a75c58 pm: remove unnecessary __weak from pm_state_set/pm_exit_post_ops
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
3d2194f11e pm: introduce HAS_PM
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Jimmy Zheng
4f26203b59 soc: riscv: andes_v5: remove redundant CONFIG_CACHE_ENABLE
Replace redundant CONFIG_CACHE_ENABLE by generic Kconfig CONFIG_ICACHE,
CONFIG_DCACHE.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
e6b1251b0d soc: riscv: andes_v5: enlarge TEST_EXTRA_STACK_SIZE
Enlarge TEST_EXTRA_STACK_SIZE for AE350 RV64 bitstream.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
b6122c358a soc: riscv: andes_v5: add Andes I/O Coherence Port option
Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle
cache coherency between cache and external non-caching master, such as DMA
controller.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
a1665cbf1c soc: riscv: andes_v5: refine Andes L2 cache
Refine source code and flush all I/D-Cache before update L2 cache register.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
65edd8433c soc: riscv: andes_v5: add Andes EXEC.IT option
Andes EXEC.IT (Execution on Instruction Table) is supported by Andes
toolchain only. Andes toolchain will replaces suitable 32-bit instructions
with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a
corresponding 32-bit instruction in look up table.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
004e00a0bd soc: riscv: andes_v5: add RV32E_CPU option
Add CONFIG_RV32E_CPU for AE350 platform integrated with Andes RV32E core,
such as N22, D23 core.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
d5c4bd6830 soc: riscv: andes_v5: support RISC-V C extension
Enable RISC-V C extension for Andes core.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
9c7f0376b8 soc: riscv: andes_v5: support PMP and USERSPACE
Enable PMP and set PMP granularity to 8 for most of ae350 bitstream.
This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
bf0e01bee2 soc: riscv: andes_v5: refine Andes PMA
Refine PMA driver and define MPU_ALIGN() to PMA granularity in
RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
de1cd06294 soc: riscv: andes_v5: update ae350 linker.ld
Synchronize ae350 linker.ld with riscv generic linker.ld and workaround
kernel object address may be 0x0 in XIP system.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Tim-Marek Thomas
5d75940ae3 boards: riscv: neorv32: Updates compatibility to neoverse v1.8.6
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).

Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
2023-07-11 18:19:55 +00:00
Tim Lin
0960bb3066 ITE: drivers/i2c: Add I2C target driver used buffer mode
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-07-11 15:50:13 +02:00
Daniel Mangum
43b057a7ce soc: neorv32: Fix spelling in reset.S
Fixes minor misspelling of instruction in the neorv32 reset.S.

Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
2023-07-09 17:50:09 +00:00
Keith Packard
710422ec5e include/zephyr: Fix linker scripts to define _end after all static RAM data
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.

Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.

Signed-off-by: Keith Packard <keithp@keithp.com>
2023-06-28 08:41:02 +00:00
Manojkumar Subramaniam
6e887e3f61 soc: riscv: Add initial support for Efinix Sapphire SoC
- It's a riscv privilege spec SoC

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2023-06-27 12:09:57 +00:00
Lucas Tamborrino
e229898caf drivers: pinctrl: esp32xx: allow internal loopback
Provides a way to use pinctrl to allow internal loopback
on a peripheral pin for testing purposes.
This is done by using output-enable on a input pin and
input-enable on a output pin.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-22 08:13:36 +00:00
Carlo Caione
fc480c9382 riscv: privileged: Add support for CLIC vectored mode
Zephyr currently only supports CLINT direct mode and CLINT vectored
mode. Add support for CLIC vectored mode as well.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-17 07:48:52 -04:00
Carlo Caione
6160383ec7 riscv: Rename RISCV_MTVEC_VECTORED_MODE to RISCV_VECTORED_MODE
Before adding support for the CLIC vectored mode, rename
CONFIG_RISCV_MTVEC_VECTORED_MODE to CONFIG_RISCV_VECTORED_MODE to be
more generic and eventually include also the CLIC vectored mode.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-17 07:48:52 -04:00
Khor Swee Aun
5bf2260e90 soc: riscv: riscv-privileged: INTEL Nios V/g support
Add support for INTEL FPGA Nios V/g RISC-V based Processors.
Also amended SOC_NIOSV_M to use ATOMIC_OPERATIONS_BUILTIN.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
2023-06-17 07:34:05 -04:00
Gerard Marull-Paretas
c59b57c0be soc: esp32*: do not enable HAS_DYNAMIC_DEVICE_HANDLES
It doesn't make sense to select this option at SoC level. This feature
is meant for subsystems/modules that need device handles to be
modifiable at runtime.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-15 10:09:26 -04:00
Carlo Caione
8eeb5c992e riscv: Move directory to *-privileged
Because the spec is "privileged" not "privilege".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-09 11:46:29 -04:00
Carlo Caione
edd3437826 riscv: Rename Kconfig symbol to *_PRIVILEGED
Rename SOC_FAMILY_RISCV_PRIVILEGE to SOC_FAMILY_RISCV_PRIVILEGED because
the spec is "privileged".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-09 11:46:29 -04:00
TOKITA Hiroshi
56f64f68ac soc: riscv: gd32vf103: Fix SYS_CLOCK_HW_CYCLES_PER_SEC to 27000000
As a result of the 11a2107d991b("riscv: timer: driver revamp") commit,
gd32vf103 no longer works properly.

In the
c9c04e491e0f("soc: riscv: Add initial support for GigaDevice GD32V SoC")
that is the first commit of implementation of this SoC,
set the CPU frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
and riscv_machine_timer divide the clock with the value of
CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.

The CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should set the timer's clock,
so I fixed to set the config as 27MHz in this PR.  Also, remove the
unnecessary CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER setting.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2023-06-05 07:08:02 -04:00
Tyler Ng
28a18ece43 soc: riscv: riscv-privilege: opentitan: Enable watchdog reset function
Adds watchdog reset as a reset source at SoC init. This is achieved by:

1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog
reset is enabled.
2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change.
3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the
change has been processed.

This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled. Note that the timer itself is not enabled here, only the
reset function.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-26 09:45:25 -04:00
Tyler Ng
e6075541ab soc: riscv: riscv-privilege: opentitan: Fix PLIC interrupts
1. Fixes the number of interrupts in OpenTitan by default. This should
   be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
   including interrupt 0.

2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
   PLIC interrupt on IRQ 11.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-26 09:45:25 -04:00
BJ Chen
215f180296 ITE: drivers/usb/device: Add USB Device Controller Support
Add USB Device Driver (usb_dc) of ITE IT82xx2

TEST=west build -p always -b it82xx2_evb
1. zephyr/sample/subsys/usb/hid
2. zephyr/sample/subsys/usb/hid-mouse

Signed-off-by: BJ Chen <bj.chen@ite.com.tw>
2023-05-26 12:40:18 +02:00
Marek Matej
4796746b5e soc: esp32: MCUboot support
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-05-25 16:15:54 +02:00
Nicolas Pitre
3aab212920 riscv: Microchip Mi-V should use built-in atomic operations
The Mi-V implements the A extension therefore it shouldn't use the C
version. The built-in version generates code with proper machine
opcodes.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-05-09 13:04:27 +02:00
Filip Kokosinski
a30862455e treewide: rename Microsemi to Microchip
Do a treewide Microsemi to Microchip rename and update obsolete links in
the board docs.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-05-04 10:47:07 +02:00
Tim Lin
1a2874affb ITE: drivers/i2c: Disable pre-detect on IT82xx2 family
Disable the hardware I2C target detection on the IT82xx2 SoC family.

Note: The register setting of I2C target detection is different in
IT81XX2 and IT82XX2 SOC.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-26 12:55:02 +02:00
Manojkumar Subramaniam
d57363bc97 riscv: refactor: Utilize the available helper macro
use helper macros from csr.h instead of inline assembly which results
in cleaner and more maintainable code

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2023-04-21 12:54:55 +02:00
Marek Matej
ddab8786fd soc: kconfig: Add config for ESP32 family
Introduce config for all ESP32 chips which
may be using different architectures but
shares common peripherals and features.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-04-19 17:12:26 +02:00
Tim Lin
71b92265d7 ITE: dts: it82xx2: Increase sram to 256KB
1. Increase sram to 256KB.
   A block sram of SCAR0~15 is 4KB.
   A block sram of SCAR16~19 is 16KB.
   A block sram of SCAR20~23 is 32KB.

2. Removed the register of RVILMCR which has no effect.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Tim Lin
491e3e6477 ITE: drivers/gpio: Add gpio_ite_it8xxx2_v2 driver
This driver is made for it82xx2 series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Tim Lin
7f3d61c608 ITE: dts: it8xxx2: Add the option of 512k flash size
Add the option of 512k flash size.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Tim Lin
051bd7098a ITE: dts: it82xx2: Add pinctrl node and kscan's pinctrl
Add the pinctrl node that has been remapped in the chip of it82xx2.
And modify kscan's pinctrl for the it82xx2.
And swap I2C default pins.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Tim Lin
e1ae5c02cb ITE: dts: it82xx2: Add GPIO general control node in it82xx2.dtsi
Add the GPIO general control node that has been remapped in the
chip of it82xx2.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Ruibin Chang
3fb097c1ff ITE: it82xx2.dtsi: add watchdog device node
With this change, it82xx2 series can use the same
watchdog driver as it81xx2 series.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2023-04-19 03:48:38 -04:00
Ruibin Chang
b9a7340ded ITE drivers/interrupt_controller: add intc_ite_it8xxx2_v2 driver
This driver is made for it82xx2 series.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2023-04-19 03:48:38 -04:00
Tim Lin
44250a9e67 ITE: soc: it8xxx2: Add it82302 and it82202 chip configuration
Add the chip configuration for it82302 and it82202.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Gerard Marull-Paretas
a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Franciszek Zdobylak
fe9d6d5737 soc: riscv: sifive: fu740: add DDR clk
Add code that initializes DDR clk alongside other clocks.

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
2023-04-12 13:05:55 +02:00
Sylvio Alves
10a7baba0e soc: esp32s3: add bluetooth support
This only adds proper HEAP and HCI definition to enable
BLE support to ESP32-S3.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-03-27 13:19:38 +00:00
Tim Lin
94ae33c20a ITE: soc/riscv/ite: policy: Add minimum residency time to enter sleep
Adding this condition will limit the minimum residency time to enter
sleep mode. This will fix tests in test\kernel\sleep\usleep.c causing
longer than expected test times due to going into sleep mode with no
time limit.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-03-16 09:16:34 +01:00
Ruibin Chang
f77f02c032 ITE drivers/sensor/vcmp/it8xxx2: add work queue for voltage comparator
Voltage comparator driver submits notifications into system work queue,
this change will make driver to use dedicated work queue, and priority
of dedicated work queue are configurable as well.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2023-03-01 09:12:49 -06:00
Sylvio Alves
f18d811c6c soc: esp32c3: fix soc architecture definition
Update ESP32-C3 architecture as IMC instead IMA.

Although not documented, ESP32-S3 supports CSR instructions.
It also needs to be enabled, otherwise build will fail.

Fixes #53555

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-02-28 12:47:56 +01:00
Jonas Otto
60b8773491 arch: riscv enable flash config
For RISCV arch, enable FLASH_SIZE and FLASH_BASE_ADDRESS config.
To avoid duplicated work, remove flash config from RISCV soc.

Signed-off-by: Jonas Otto <jonas@jonasotto.com>
2023-02-28 10:29:03 +01:00
Tim Lin
00e6c19ab5 ITE: drivers/adc: Add config of ADC reference voltage full-scale 3300mV
This option can enable ADC internal reference voltage as
full-scale 3300mV.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-02-23 08:59:54 +01:00
Khor Swee Aun
5b17a6da84 soc: riscv: riscv-privilege: INTEL NIOSV support
Add support for INTEL FPGA NIOSV RISCV based Processors.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
2023-02-20 09:29:13 -05:00
Shawn Nematbakhsh
f0e790c66b soc: riscv: riscv-privilege: Add support for OpenTitan SOC
Add support for OpenTitan, an open source silicon root of trust.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-27 19:25:26 +09:00
Dino Li
a41a4e5e24 espi: it8xxx2: enable espi transaction interrupt
The interrupt is used to wake up EC from low power mode.
So EC does not defer eSPI bus while transaction is accepted.
Fixes EC host commands slow issue.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2023-01-18 09:55:44 +01:00
Ruibin Chang
344c9c67f9 ITE drivers/pinctrl/it8xxx2: extend pinctrl driver for kscan pins
Extend pinctrl driver for kscan pins.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2023-01-14 09:22:39 +01:00
Sylvio Alves
cff71c8d2b driver: systimer: increase esp32c3 tick resolution
hal_espressif systimer HAL calls are based on 1MHz reference.
This changes systimer driver to allow max clocking reference of 16MHz
and increases soc tick resolution by reducing min delay interval.

This also sets all ESP32-C3 socs to 16MHz hardware cycles reference.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-01-04 14:24:25 +01:00
Dino Li
2ecdd8fa89 ITE soc/it8xxx2/linker: add sections for hw sha256 calculation
IT8XXX2 HW support sha256 calculation, and its calculation is
faster than FW. We place SHA256 message, hash and key data
(total 512bytes) in RAM. If we enable hw sha256, because
HW limits, the sha256 data must place in first 4KB of RAM.
We add sections for hw sha256 calculation in linker.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-12-14 09:51:25 +01:00