Commit graph

503 commits

Author SHA1 Message Date
Gerard Marull-Paretas
7da6342dff soc: riscv: virt: reorganize SoC folder
Move out of riscv-privileged, and convert to single SoC (no
family/series).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
b7b19b8b05 soc: riscv: neorv32: reorganize SoC folder
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
7a44806a53 soc: riscv: s/litex-vexriscv/litex_vexriscv
To be consistent with other SoCs in the same folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
4a0d880350 soc: riscv: ite: reorganize SoC folder
Follow the vendor structure [1]:

- Family: ITE Embedded Controller SoCs
- Series: IT8XXX2
- SoCs: IT81202BX, IT81202CX, etc.

[1]: https://www.ite.com.tw/en/product/category?cid=1

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
8027689392 soc: riscv: andes_v5: reorganize SoC folder
Split out from riscv-privileged folder, and create a new family.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
87f3b07292 soc: riscv: starfive_jh71xx: reorganize SoC folder
Move it out from RISC-V privileged folder, and create a standalone
family.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
5a98d87335 soc: riscv: gd32vf103: reorganize SoC folder
Move things out from riscv-privileged, and create the new RISC-V GD32
family. New family folder follows the <vnd>_<family> naming convention.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
72e52a06aa soc: riscv: telink_b91: reorganize SoC folder
Reorganize following the hierarchy found in the vendor website [1]:

- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518

Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].

[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
     B91_Generic_Starter_Kit_Hardware_Guide/

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
d8c0cc2e35 soc: riscv: introduce temporary RISCV_PRIVILEGED_STANDALONE
So that SoCs can be ported outside of riscv-privileged folder, setting
their own family name. This will be removed once all SoCs are ported.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
0106e8d14c arch: riscv: introduce RISCV_PRIVILEGED
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.

Note that the SoC family naming scheme will be fixed in upcoming
commits.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
9a35ad858c soc: riscv: gd32vf103: move nuclei CSR header
The header is common to all Nuclei based cores (not strictly related to
RISCV privileged spec). Since only GD32VF103 uses a Nuclei core, move
the file to its SoC folder.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Gerard Marull-Paretas
6443c50bd0 soc: riscv: move privileged code to common folder
Add a new riscv/common directory where to store common code between
SoCs, e.g. those implementing the privileged spec.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Sylvio Alves
b19c164e7b soc: espressif: add common linker tls entry
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-01-08 15:09:48 +01:00
Yong Cong Sin
c328a38a94 soc: riscv: add support for Renode Virt RISCV32 SoC
Add a beef-ed up version of Renode's `riscv_virt` SoC

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-08 12:35:10 +01:00
Ren Chen
5762d022dc drivers: usb: usb_dc_it82xx2: optimize the basic/extend endpoints control
This commit refactors the basic and extended endpoint control functions to
enhance readability.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2023-12-20 11:15:38 +01:00
Ren Chen
e23ae3b678 drivers: usb: usb_dc_it82xx2: refactor usb driver with macros
Refactor the code using macros to enhance readability.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2023-12-20 11:15:38 +01:00
Conor Paxton
dc5cf9cb1c soc: mpfs: describe the correct amount of irqs available.
Microchip's PolarFire SoC (MPFS) has 186 available interrupts.
Fix the Kconfig symbols.

While we're at at: remove commented out code

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
2023-12-06 17:54:29 +00:00
Chen Xingyu
3f7e73416d soc: riscv: privileged: efinix-sapphire: Enable CONFIG_RISCV_HAS_CPU_IDLE
In an earlier commit, the riscv-privileged level implementation of
`arch_cpu_idle()` is not included unless `CONFIG_RISCV_HAS_CPU_IDLE` is
enabled.

This commit ensures the option is enabled on all the existing CPUs, thereby
maintaining the existing behavior.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
2023-11-28 15:34:06 +01:00
Chen Xingyu
34d2c4d6b2 soc: riscv: privileged: Conditionally override arch_cpu_idle()
The current configuration comes with a common implementation of
`arch_cpu_idle()` for the whole riscv-privileged family, utilizing the
`WFI` instruction to place the CPU into a light sleep state, with the
assumption that it will be awakened later by interrupts such as SYSTICK.
However, this approach is not always effective, particularly in scenarios
where the SYSTICK is not a valid wake source.

This commit uses `CONFIG_RISCV_HAS_CPU_IDLE` as the build condition of the
family-level `idle.c`, allowing CPUs that do not enable this option to
fallback to a generic arch-level implementation in
`arch/riscv/core/cpu_idle.c`.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
2023-11-28 15:34:06 +01:00
Sylvio Alves
ca346ba216 soc: esp32: call reset cause reason init
Reset cause reason was not initalized properly, making
hwinfo feature not to work as expected.

Fixes #65634

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-11-27 19:59:45 +01:00
Yong Cong Sin
e538b0e5a6 drivers: plic: support multiple instances for multi-level
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 18:20:43 +01:00
Tim Lin
f1dc11174c ITE: drivers/i2c: Add a property for I2C located channel
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-11-08 10:08:28 +01:00
Torsten Rasmussen
10fea41f5c cmake: riscv: update riscv SoC to use SOC_LINKER_SCRIPT variable
This commit updates all riscv SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-03 11:01:23 +01:00
Ederson de Souza
928e22c302 soc/riscv/riscv-ite/it8xxx2: Support DEVNULL_REGION
it8xxx2 uses a custom linker script, which was not updated on
dfb3674c4c. This patch naively updates it
to support DEVNULL_REGION.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-11-01 18:48:24 -04:00
Yong Cong Sin
d7302f417e irq: relocate multi-level irq out of irq.h
Relocate multi-level interrupts APIs out of `irq.h` into
a new file named `irq_multilevel.h` to provide cleaner
separation between typical irq & multilevel ones.

Added preprocessor versions of `irq_to_level_x` as `IRQ_TO_Lx`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-30 11:43:39 -04:00
Michael Arnold
973e226bfd arch: Enable ramfunc feature on RISC-V PRIVILEGE SOC family
Allow to place functions in ram.

Signed-off-by: Michael Arnold <marnold@baumer.com>
2023-10-25 17:35:07 +02:00
Sylvio Alves
3f5ea785f2 linker: esp32: fix linker to enable proper MMU usage
ESP32 flash_mmap() function requires `_rodata_reserved_start` address
to be at the beginning of RODATA. This allows adding memory-mapped flash
areas.

Fixes #52764

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-10-25 09:57:48 +02:00
Tim Lin
35e3dfed2d ITE: soc: Add the variant of it82002aw
This variant uses the same die as IT82202/IT82302 series and has
a pinout compatible with IT513xx series packages.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-10-20 15:07:28 +02:00
Sylvio Alves
4b5331ba45 linker: esp32: move snippets-section within rom boundary
This will guarantee that application snippets will be placed
into ROM section properly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-10-13 13:10:22 +03:00
Detlev Zundel
42ea06cf21 soc: xtensa,riscv: esp32c3: Fix SOC_PART_NUMBER choices
Add the ESP32-C3-WROOM-02 modules with 4 or 8 MiB flash. The
temperature and antenna / connector variants are not mentioned
explicitely as they do not influence the software.

Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
2023-10-06 12:24:49 +01:00
Yong Cong Sin
93cbfcfee9 board: riscv: qemu: increase ndev of PLIC to 1024
Increase the `ndev` of PLIC to the max of 1024 from 53, as
supported by the RISCV PLIC. The total number of IRQs is now
1035(1024 + 11), up from 64(53 + 11).

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-05 06:10:06 -04:00
Yong Cong Sin
5b9f82668b riscv: telink_b91: fix compilation
Fix compilation failure due to multilevel interrupt.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-18 13:03:45 -04:00
Sylvio Alves
f5fa4b3bcd soc: espressif: provide VMA to rodata and text by default
Flash segments require VMA to proper work. Executing from LMA
is not possible. Current implementation did not take into account
runtime iterable rom sections that any application could implement.
In the above cenario and as reported in the issue below, ESP32 won't run
when those ROM sections are created in application level.

This change make sure all flash segments are properly mapped
accordingly.

Fixes #61834

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-09-18 10:38:03 +01:00
Gerard Marull-Paretas
aaeb0a672e toolchain: only include <zephyr/toolchain.h>
It is wrong to use toolchain-specific header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Huifeng Zhang
2c22e83dfb include: arch: arm: Remove aarch32 directory
This commit follows the parent commit work.

This commit introduces the following major changes.

  1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
    to the 'include/zephyr/arch/arm' directory.

  2. Change the path string which is influenced by the changement 1.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-09-13 10:08:05 +01:00
Tim Lin
8a779fc706 ITE: drivers/i2c/target: Introduce I2C target transfer using PIO mode
Introduce I2C target transfer using the PIO mode. Add an option
"target-pio-mode" in the yaml file, determined by the DTS, to dictate
whether I2C target transfer uses the PIO mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-09-07 09:43:06 +02:00
Tim Lin
3ae9a358fb ITE: drivers/i2c/target: Disable the timeout setting
Disable the timeout setting when both the clock and data are
in a low state. This allows for I2C host clock stretching
without a timeout limit.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-09-07 09:43:06 +02:00
Almir Okato
af3b04238e soc: espressif: adjust memory organization on linker
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Dino Li
003e0be6fb it8xxx2/linker: append h2ram_pool section at the end of used memory
Since __sha256_ram_block section must in the first 4KB,
h2ram_pool section is no longer included first inside the
RAMABLE_REGION.
Append h2ram_pool section at the end of used memory, so gap
due to alignment is still available for newly added variables.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2023-08-31 10:20:17 +02:00
Gerard Marull-Paretas
47fba91367 soc: riscv: telink_b91: add missing init.h, devicetree.h
File was including device.h for nothing, it needs init.h and
devicetree.h instead.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:51:57 +02:00
Tim Lin
ed37374dac ITE: drivers/pwm: Add the flag of PWM output open-drain mode
This flag is used when the PWM output is set to open-drain mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-08-25 10:31:42 +02:00
Gerard Marull-Paretas
3118a8c05c soc: riscv|xtensa: esp32: add support for sys_poweroff
Implement the sys_poweroff hook for all ESP32 SoCs based on the previous
SOFT_OFF implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-15 10:15:38 -07:00
Yong Cong Sin
84b86d9b0c soc: riscv: Add ability to use custom sys_io functions
Add Kconfig RISCV_SOC_HAS_CUSTOM_SYS_IO symbol so that a riscv
SoC can set to specify that it has a custom implementation for
sys_io functions.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-07-26 09:43:59 +02:00
Marek Matej
6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
Gerard Marull-Paretas
55f5a75c58 pm: remove unnecessary __weak from pm_state_set/pm_exit_post_ops
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
3d2194f11e pm: introduce HAS_PM
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Jimmy Zheng
4f26203b59 soc: riscv: andes_v5: remove redundant CONFIG_CACHE_ENABLE
Replace redundant CONFIG_CACHE_ENABLE by generic Kconfig CONFIG_ICACHE,
CONFIG_DCACHE.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
e6b1251b0d soc: riscv: andes_v5: enlarge TEST_EXTRA_STACK_SIZE
Enlarge TEST_EXTRA_STACK_SIZE for AE350 RV64 bitstream.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
b6122c358a soc: riscv: andes_v5: add Andes I/O Coherence Port option
Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle
cache coherency between cache and external non-caching master, such as DMA
controller.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
a1665cbf1c soc: riscv: andes_v5: refine Andes L2 cache
Refine source code and flush all I/D-Cache before update L2 cache register.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00