Commit graph

250 commits

Author SHA1 Message Date
Gerard Marull-Paretas
95fb0ded6b kconfig: remove Enable from boolean prompts
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:

sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Henrik Brix Andersen
2ffce62f61 soc: arm: nxp: kinetis: fix pinctrl compilation for ke1xf SoC series
The NXP KE1xF SoC series does not support neither slew rate nor open
drain PORT configuration registers.

Fix pinctrl compilation for the KE1xF by defining dummy register macros
for the SRE and ODE registers.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-03-07 13:52:12 -06:00
Daniel DeGrasse
bdbb72a95a soc: kinetis: Add common pinctrl include file
Add pinctrl include file to define SOC specific pinctrl_soc_t structure,
used to store pin configuration for pinctrl driver

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-03 13:00:20 -06:00
Flavio Ceolin
78454e5e93 pm: Rename pm_power_state_exit_post_ops
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-02-23 07:33:46 -05:00
Flavio Ceolin
89fee61b43 pm: Rename pm_power_state_set
Aligning with the rest of PM API, replace pm_power_state_set with
pm_state_set.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-02-23 07:33:46 -05:00
Carlo Caione
c5894df5ec pm: Change parameters of pm_power_state_{set,exit_post_ops}
Just pass state and substate_id instead of the whole info structure
pointer.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-02-21 20:58:01 -05:00
Carlo Caione
11f1dd2370 pm: Reference pm_state_info only by pointer
It's unnecessary to move the pm_state_info around by value, just use a
pointer.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-02-21 20:58:01 -05:00
Daniel Leung
aa20e081d2 arm: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Tom Burdick
73f343c51e board: Adds RDDRONE-FMUK66 board support package
Adds required LQ18 part number to the kinetis K66 series

Signed-off-by: Tom Burdick <tom.burdick@electromatic.us>
2021-11-02 13:17:44 -05:00
Maureen Helm
b0cdef3c25 drivers: adc: Refactor drivers to use shared init priority
Refactors all of the ADC drivers to use a shared driver class
initialization priority configuration, CONFIG_ADC_INIT_PRIORITY, to
allow configuring ADC drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.

The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The
exceptions are lmp90xxx, mcp320x, and mcux_adc16 drivers which have
dependencies on GPIO, SPI, and/or DMA drivers and must therefore
initialize later than the default device priority.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-20 07:33:44 -04:00
Maureen Helm
8302e5e21c soc: arm: Configure serial driver init priority for NXP SoCs
Configures the default serial driver initialization priority for NXP
SoCs to ensure that serial drivers initialize after clock control
drivers.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-17 10:58:09 -04:00
Jordan Yates
fdeaa9103e random: deprecate XOROSHIRO_RANDOM_GENERATOR
Deprecate the xoroshiro128+ PRNG algorithm in favour of xoshiro128++.
xoshiro128++ is a drop-in replacement which is invisible from the user
perspective.

xoroshiro128+ is unsuitable because it is explicitly a floating-point
PRNG, not a general-purpose PRNG. This means that the lower 4 bits of
the output are actually linear, not random (from the designers,
https://prng.di.unimi.it/). This means 1/8th of the generated data is
not random.

Additionally, xoroshiro128+ is not a 32bit algorithm, it operates on
64bit numbers. For the vast majority of Zephyr devices, this makes the
PRNG slower than it needs to be. The replacement (xoshiro128++) is
32bit, with no loss in state space (still 128 bit).

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-08-05 11:24:44 +02:00
Johann Fischer
6e1e2fba82 soc: replace USB configuration option with USB_DEVICE_DRIVER
Replace USB configuration option with USB_DEVICE_DRIVER
since on the SoC level the specific driver is selected.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-08-03 19:00:12 -04:00
Erwan Gouriou
acba0cd55a soc/arm: power: Leftover from pm hooks conversion to __weak
In commit "pm: Fix weak linkage symbols" (PR #35274),
PM SoC hooks were converted to __weak to avoid clash with
new definition of these symbols in subsys/pm/power.c.

In this process, few SoCs were missed.
Fix this.

#37226

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-07-27 07:18:05 -04:00
Henrik Brix Andersen
316cb25db4 soc: arm: nxp: kinetis: ke1xf: add support for power management
Add power management support (runtime-idle and suspend-to-idle)
support for the NXP Kinetis KE1xf SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Henrik Brix Andersen
7436432f2e soc: arm: nxp: kinetis: ke1xf: enable lptmr as timer
Enable the NXP Kinetis Low Power Timer (LPTMR) OS timer driver when
power management is enabled as the Arm SysTick timer cannot wake up the
KE1xF from deep sleep.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Henrik Brix Andersen
937c2c8dfd soc: arm: nxp: kinetis: ke1xf: keep the sirc running in low-power mode
Keep the Slow Internal Reference Clock (SIRC) running in low-power
mode.

This allows peripherals that needs to remain operative in low-power
mode to use the SIRC as clock source.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Henrik Brix Andersen
5fcb13aea3 soc: arm: nxp: kinetis: ke1xf: determine hw clock cycles/sec from dts
Determine the default CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from devicetree
when using the Arm SysTick hardware timer.

When the NXP KE1xF SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-14 22:54:34 +03:00
Henrik Brix Andersen
493c909a33 soc: arm: nxp: kinetis: kwx: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KWx SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
d16d34b152 soc: arm: nxp: kinetis: kv5x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KV5x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
6b811443d4 soc: arm: nxp: kinetis: kl2x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KL2x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
01f62a08f3 soc: arm: nxp: kinetis: k8x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP K8x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
f6a84125b6 soc: arm: nxp: kinetis: k2x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP K2x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
3d20888359 soc: arm: nxp: kinetis: ke1xf: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP KE1xF SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
e22ce47c4f soc: arm: nxp: kinetis: k6x: indicate presence of RCM
Indicate presenence of the Reset Control Module on the NXP K6x SoC
series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-07-08 09:33:32 -05:00
Henrik Brix Andersen
eb9cf9e0dc soc: arm: nxp: kinetis: k2x: remove MPU support
Remove (disabled) MPU support for the NXP Kinetis K2x. At least the
MK22F51212, which is the only K2x supported by Zephyr so far, does not
contain an MPU.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-05-26 18:14:03 -05:00
Hake Huang
0062372af1 adc: add soc config for adc
update k8x series to support edma and pit

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2021-05-07 08:23:49 -05:00
Bradley Bolen
3b6707f140 arch: arm: aarch32: Use mpu headers from common aarch32 location
The mpu headers moved in order to support the Cortex-R mpu in later
commits.  Use the new locations.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2021-05-06 19:39:09 +02:00
Henrik Brix Andersen
a865b1bb49 soc: arm: nxp: ke1xf: use clock nodes for NXP Kinetis SCG clocks
Use a combination of fixed-clock and fixed-factor-clock devicetree
nodes for describing the clock dividers/multipliers of the NXP Kinetis
System Clock Generator (SCG) present in the KE1xF SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-03-31 11:56:13 -05:00
Mikkel Jakobsen
fbfd75e19a soc: nxp: kl2x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.

The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
2e9500359f soc: nxp: k2x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
f0c01561fe soc: nxp: k8x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
f218bec877 soc: nxp: kv5x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig.

The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
68e8a4870d soc: nxp: kwx: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig.

Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
f674e82ac4 soc: nxp: k6x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
1f59da40bd soc: arm: nxp: remove unused clock defines
SYSCLK_DEFAULT_IOSC_HZ and BUSCLK_DEFAULT_IOSC_HZ are
not used anywhere in the tree and can be removed

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
b5c09de995 soc: nxp: k2x: enable DAC driver
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K2x SoC series.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-02 16:27:47 -06:00
Ryan Holleran
b417bb85d2 dts: nxp_k2x: Correct and enable MCG clock controller binding
nxp_k2x.dtsi: Corrects Multipurpose Clock Generator binding
to utilize nxp,kinetis-mcg. Assign MCG to FlexTimer devices.
Enable FlexTimer clocks via System Integration Module clock
gate control registers.

Kconfig.defconfig.mk22f12: Enable default use of
CLOCK_CONTROL_MCUX_MCG when CLOCK_CONTROL is selected.

Signed-off-by: Ryan Holleran <rhollerar@gmail.com>
2021-02-15 08:14:06 -05:00
Henrik Brix Andersen
8167134f05 drivers: pwm: add driver for the NXP Kinetis Pulse Width Timer (PWT)
Add PWM capture driver for the NXP Kinetis Pulse Width Timer (PWT).

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2021-01-20 08:05:57 -06:00
Henrik Brix Andersen
bd25cb73fe soc: arm: nxp: ke1xf: enable ACMP support
Enable support for the NXP MCUX Analog Comparator (ACMP) in the NXP
KE1xF SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-12-17 08:54:33 -06:00
Nicolai Glud
bc72b67a5d dts: clocks: kinetis: set pllfll and er32k clock settings from dts
Setup osc clock settings from dts.

Signed-off-by: Nicolai Glud <nicolai.glud@prevas.dk>
2020-09-29 14:05:50 -05:00
Tomasz Bursztyka
e18fcbba5a device: Const-ify all device driver instance pointers
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.

A coccinelle rule is used for this:

@r_const_dev_1
  disable optional_qualifier
@
@@
-struct device *
+const struct device *

@r_const_dev_2
 disable optional_qualifier
@
@@
-struct device * const
+const struct device *

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Hake Huang
ebd0a3759e counter: enable k6s pit support support
enable k6s pit counter support

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-08-21 14:27:59 -05:00
Hake Huang
f976de4767 counter: enable pit support for k8x series
enable PIT in k8x series

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-08-21 14:27:59 -05:00
Henrik Brix Andersen
02027126f8 soc: arm: nxp: ke1xf: enable edma support
Enable eDMA support.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-07-21 08:56:51 -05:00
Hake Huang
10fc7a38cc dma: add EDMA MCUX support for RT and k6s
tested on mimxrt1060_evt
  MEMORY_NOCACHE is needed
test on frdmk64f
  special test slot need configure with
  CONFIG_DMA_TEST_SLOT_START

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-06-12 13:03:28 -05:00
Lukasz Majewski
27b4e63d4f clk: k6x: Enable High Speed RUN (HSRUN) mode for K66F SOC
The NXP's Kinetics K66F is able to run with max frequency of 180MHz.
To achieve this goal the SMC's PMPROT and PMCTRL registers need to be
adjusted.

On the contrary the K64F doesn't support HSRUN run mode.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-06-10 13:02:22 -05:00
Lukasz Majewski
b25490d22b k6x: Kconfig: Add CONFIG_K6X_HSRUN option for K66F
This option enables support for High Speed RUN operation mode for
K66F. The K64F SoC doesn't support this mode.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-06-10 13:02:22 -05:00
Lukasz Majewski
a341d4cd43 clk: k6x: Modify clock_init to enable external RMII clock source
This change enables the RMII external clock source at the clock
initialization function.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-06-10 13:02:22 -05:00