Add ipm driver to use Inter Processor Interrupts
on Xilinx ZynqMP platform. This patch also adds sample
application that shows use of xlnx ipm driver.
This driver uses default arm gic interrupt controller
and works only for lockstep mode of cortex-r5f
cluster for now.
In split mode the cortex-r5 cluster will
have two r5f cores and they are expected to work in AMP
mode. If both r5f cores run simultaneouly, only one of
the core is able to receive IPI interrupts at this time
and it will be the one that started later. In future
this limitation shall be removed.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
This change introduces a new PWM driver for all CC13/26xx SoC.
See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed
usage instructions.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Allow properties 'regulator-min-microvolt' and 'regulator-max-microvolt'
for fixed regulators: Note: they should be equal.
Add simple functions for getting list of allowed and count of voltages.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Possible situation is that in some driver, devices can be controlled in
different ways: in some, we can only turn the power on or off, in others,
we can only control the voltage, and in some, we can control power supply
or voltage level. There may also be devices where there is no control
over power supply at all. A clear example of this can be eMMC devices
where the voltage is usually fixed and they are always powered on.
However, we would like to have a common code for controlling all the
mentioned types of devices, at least the driver shouldn't worry about the
implementation details of voltage regulators. Therefore, there may exist
empty regulators - regulators that only contain information about the
supported voltage, and we cannot change anything in them. The device tree
node description for such a regulator is only necessary for compatibility
with other regulators. Hence, we need to add the possibility of the
existence of such a dummy fixed-regulator.
In this commit, support for a fixed dummy regulator without the ability
for any control has been added. Note that such support also exists in the
Linux kernel. In other words, the logic of the fixed regulator has been
aligned with the logic of the fixed regulator inside the Linux kernel.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Although there are no in-tree users, we will deprecate the
`facebook` vendor prefix and add `meta`.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Add watchdog support to ELkhart Lake board basically copying
configuration from Raptor Lake.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Since we do not have any in-tree users, we will skip the
deprecation process for `facebook` and add `meta`.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Disabled uart0 and uart1 by default in alder_lake.dtsi and enable only
for intel_adl_crb board.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This commit adds input clock selection to the RTC driver. This
is required to allow for the real hardware to operate. The
QEMU emulated hardware ignores the input clock settings.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
INPUT_REL_WHEEL is the code that normally refer to scroller wheel, which
probably makes a bit more sense in this context, use that instead of
INPUT_REL_Y.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Enable CANFD for rt11xx by including nxp,flexcan-fd
compatibility for all CANFD capable CAN with associated
properties.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
This commit instantiates the counter peripheral.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Change the gpio-keys and zephyr,gpio-keys so that they can both be used
with the input subsystem driver. Make the zephyr,code property optional
so that existing out of tree board can still use this node with their
custom code, but change everything else so that an existin gpio-keys
node can be used with the input driver as long as the codes are defined.
From the application perspective, this means that the application can
still use the GPIOs directly, the input specific driver only gets
enabled if CONFIG_INPUT is enabled and the driver can always be turned
off manually.
This makes gpio-keys behave the same as gpio-leds with CONFIG_LED.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The controller and the driver support two hardware configurations:
- one three-channel (RGB) LED
- or three single-channel LEDs
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Some boards may have connected the enable pin of the chipset to a GPIO.
On these boards, it is necessary to configure and set this GPIO before
using the chipset, otherwise the I2C circuitry is disabled.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add support for LP5009, LP5012, LP5018 and LP5024 devices which only
differ by the number of LEDs they can control.
Also, update application sample to run on all these new supported
devices.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
UART controllers present on Ambiq SoCs implement a PL011 compatible
interface, with some minor differences that require certain quirks.
To support them a dedicated compatible is needed.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Adds a new I2C shim driver for Intel SoCs. Builds upon the SEDI bare
metal I2C driver in the hal-intel module.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Sometimes, channel C may write wrong register to the target device.
This issue occurs when FIFO2 is enabled on channel C. The problem
arises because FIFO2 is shared between channel B and channel C.
FIFO2 will be disabled when data access is completed, at which point
FIFO2 is set to the default configuration for channel B.
The byte counter of FIFO2 may be affected by channel B. There is a
chance that channel C may encounter wrong register being written due
to the FIFO2 byte counter wrong write after channel B's write operation.
The current workaround is that channel C cannot use FIFO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The system still takes both prefixed and unprefixed dt-bindings files,
but let's use zephyr/ prefixed in the examples and documentation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
On ACE a seperate, soc specific, interrupt mask needs to be enabled
to unmask the interrupt. Do so for GPDMA.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
SPI driver is current working for common SPI devices.
However, addressable LED like WS2812 requires MOSI line to be
default LOW during initialization. This PR adds such option.
This has no effect on common SPI operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Modify the NPCX driver erase method to allow 0x1000 byte size erases
along with 0x10000 byte size erases based on input parameters
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add initial support for NXP S32 GMAC/EMAC:
- it's a copy-implementation with DMA data buffers and buffer
descriptors in non-cached memory (buf len and ring size configurable)
- PHY interface selection only implemented for S32K3 devices as it is
SoC-specific
- no PHY driver integration, it works as a fixed link with speed/duplex
configured through devicetree
- supports multicast hash filtering, promiscuous mode, MAC loopback
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Change the eth-phy definition so that the phy is pointed by a phandle
rather than a child node, make the phy device a child of mdio. This
makes more sense from a devicetree hirearchy where the phandles have to
be initialized before the device itself, allows keeping the priorities
in check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Make ethernet phys childs of the mdio device and move the mdio device up
a level on the tree. That makes the device hierarchy coherent with the
required initialization priority and allows keeping the sequence in
check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add option to use (by defining the `wake-gpios` devicetree properties)
an additional signal line between SPI master and SPI slave that allows
the latter to stay in low-power state and wake up only when a transfer
is to occur.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
