Commit graph zephyr/dts
Author SHA1 Message Date
Tien Nguyen
b8215ec539 dts: bindings: Add CPU device bindings for Cortex-R8
This commit adds device bindings for Cortex-R8

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2025-06-24 14:22:43 +02:00
Fabio Baltieri
f2934c8b8a bindings: uart-bridge: add missing base include
Add missing base include for the uart-bridge binding.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2025-06-24 14:19:24 +02:00
Phi Tran
3fa9495172 drivers: gpio: add gpio interrupt support for RX130
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
2025-06-24 14:18:41 +02:00
Phi Tran
da38a779ea drivers: external interrupt: add external interrupt support for RX130
Add support for external interrupt on RX130.

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
2025-06-24 14:18:41 +02:00
Tatsuya Ogawa
5560c9f12a drivers: interrupt_controller: Add interrupt controller support for RX130
Add interrupt controller driver support for RX130 series

Signed-off-by: Tatsuya Ogawa <tatsuya.ogawa.nx@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2025-06-24 14:18:41 +02:00
Anıl Kara
34b06f89fe dts: arm: adi: Add timer nodes to max32657
Add nodes timer0 to timer5. Add pwm and counter subnodes.

Signed-off-by: Anıl Kara <anil.kara@analog.com>
2025-06-24 09:15:07 +02:00
Laurentiu Mihalcea
44f346e6d7 dts: bindings: dai-esai: allow pinctrl-related properties
Allow pinctrl-related properties to be specified in the ESAI
DT node.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2025-06-24 09:13:45 +02:00
Laurentiu Mihalcea
1f483b37ea drivers: clock_control: mcux_ccm: support QM/QXP's ESAI/AUD_PLL1 clocks
Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the
AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2025-06-24 09:13:45 +02:00
Francois Ramu
aac2c5c568 dts: arm: stm32 reg definition for the st,stm32-qspi compatible
The st,stm32-qspi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32F412, stm32F7, stm32L4, stm32H7, stm32WB series.
qspi is addressing max 256 MBytes from 0x90000000.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-24 09:13:33 +02:00
Francois Ramu
ec9f74f57d dts: bindings: flash controller size of the stm32 qspi nor
This change adds the size in Bits of the flash nor memory
for the st,stm32-qspi-nor compatible

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-24 09:13:33 +02:00
Peter Fecher
f559f588da dts: nxp_imx8ml_m7: Add i2c Devicetree nodes
Add i2c DeviceTree nodes for use with the
Coretex M7 on the NXP imx8ml.

Signed-off-by: Peter Fecher <p.fecher@phytec.de>
2025-06-24 09:13:04 +02:00
Benjamin Perseghetti
4d91f6c3ed drivers: sensor: icm42688 enable fifo-hires in DT
Allow setting fifo-highres from DT, also unify the
naming of all registers and expand to a more complete list.

Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
2025-06-23 16:29:32 -05:00
Benjamin Perseghetti
5c9d6d44f3 drivers: sensor: icm42688 add axis_align in DT
Introduces the ability to set static axis
alignment of a sensor from DT params.

Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
2025-06-23 16:29:32 -05:00
Duy Nguyen
92a631e836 drivers: i2c: Add support i2c driver for Renesas RX MCU
Add initial support for i2c on Renesas RX MCU
This driver is controlling the RIIC HW of RX MCU for i2c bus
interface on Zephyr
Only master mode is supported

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-06-23 16:26:51 -05:00
Khaoula Bidani
7fe048cae1 dts: arm: st: u3: add i2c
Add I2C nodes to STM32U3

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-23 12:33:52 -07:00
Sergei Ovchinnikov
34188c4336 dts: bindings: add npm1304 extracting common from npm1300
Add nPM1304 device tree bindings. Extract the properties common to
nPM1300 and nPM1304 into npm13xx-common files.

Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
2025-06-23 16:19:43 +01:00
Dave Joseph
fb3c562644 dts: arm: ti TISCI DMSC support for AM2434 EVM
Device tree edits to add DMSC system controller support for
AM2434 EVM. This includes the addition system-controller and
secure-proxy mailbox nodes in arm46x_main.dtsi.

Signed-off-by: Dave Joseph <d-joseph@ti.com>
2025-06-23 15:54:34 +01:00
Dave Joseph
95c20c338c drivers: firmware: TISCI driver support
Added TISCI driver for supported devices using the binding ti,k2g-sci.
This is used to communicate via the secury proxy channel for clock,
resource and power domain management.
Refer: https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/TISCI_header.html

Signed-off-by: Dave Joseph <d-joseph@ti.com>
2025-06-23 15:54:34 +01:00
Bjarki Arge Andreasen
4c3671aea3 dts: vendor: nordic: nrf54h20.dtsi: disable cpurad_hsfll
The cpurad_hsfll is not yet supported by the NRFS DVFS service,
disable it to prevent driver from being loaded.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-06-23 15:47:01 +01:00
Hao Luo
4a9412b5d4 drivers: adc: add dma support for ambiq adc driver
This commit adds dma support for ambiq adc driver

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-06-23 15:45:44 +01:00
Khaoula Bidani
022ad6839a dts: arm: st: u3: add gpdma
Add GPDMA support to STM32U3

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-23 13:42:19 +02:00
Jamie McCrae
2a674977dd dts: vendor: nordic: nrf54l*: Fix GPREGRET register addresses
Fixes these peripheral's to have the correct addresses

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-23 09:46:33 +02:00
Tony Han
685375fbc5 dts: microchip: sam: add I2C (FLEXCOM submodule) nodes to sama7g5.dtsi
Each of the 12 FLEXCOM instances supports working in TWI (I2C) mode.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-06-22 18:44:04 -07:00
Tony Han
6243ff43c4 dts: microchip: sam: add all USART (FLEXCOM submodule) to sama7g5.dtsi
SAMA7G5 has 12 FLEXCOM instances and each of them supports working in
USART mode.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-06-22 18:44:04 -07:00
Tamas Jozsi
2c43a00f65 boards: fix Bluetooth LE support on the SparkFun ThingPlus Matter MGM240
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
2025-06-21 15:31:36 +02:00
Tamas Jozsi
e4dc7c9fb1 soc: silabs: Add support for the MGM240SD22VNA
Also introduce the framework to support other
Silicon Labs modules.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
2025-06-21 15:31:36 +02:00
Camille BAUD
8c385be293 soc: bflb: enable clock_control for bl60x
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-21 10:40:20 +02:00
Camille BAUD
46b5d05ae1 drivers: clock_control: Introduce bl60x clock driver
This introduces a clock_control driver for bl60x

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-21 10:40:20 +02:00
Francois Ramu
d63b6e774f dts: arm: stm32 reg definition for the st,stm32-ospi compatible
The st,stm32-ospi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32H7, stm32L4plus, stm32L5, stm32U5 series.
ospi1 is addressing max 256 MBytes from 0x90000000
ospi2 is addressing max 256 MBytes from 0x70000000

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-20 14:41:41 -05:00
Francois Ramu
c550baecb6 dts: bindings: flash controller size of the stm32 ospi nor
This change adds the size in Bits of the flash nor memory
for the st,stm32-ospi-nor compatible.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-20 14:41:41 -05:00
Francois Ramu
66b85e5a81 dts: bindings: flash controller stm32-xspi-nor compatible
Update the description of the bindings to match the
xspi-nor-flash node properties: size in expressed in Bits

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-20 14:41:41 -05:00
Camille BAUD
3787be931e drivers: display: Introduce SSD1363
This introduces a driver for the SSD1363 PMOLED controller

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-20 14:41:31 -05:00
Mario Paja
0637ec4821 drivers: i2s: stm32 sai add mclk-divider property
This property enables the user to configure the Master Clock Divider.

Signed-off-by: Mario Paja <mariopaja@hotmail.com>
2025-06-20 13:26:14 -04:00
Mathieu Choplain
f8db99339e dts: arm: st: stm32n6: change pinctrl binding
Use the new and appropriate "st,stm32n6-pinctrl" compatible for the pinctrl
in DTSI for STM32N6 series.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-20 13:21:55 -04:00
Mathieu Choplain
58baaa395f bindings: pinctrl: stm32: add binding for STM32N6 series pinctrl
Add a new binding for the pinctrl controller of STM32N6 series.

The specificity of this series is the "I/O retime" feature not present on
other series. This new binding exposes pinctrl properties to configure this
feature.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-20 13:21:55 -04:00
Khaoula Bidani
1cfcdcb804 dts: arm: stm32u3: add entropy node as Random Number Generator
Add the true Random Number Generator (RNG) node for stm32u3 socs.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-20 08:52:15 +02:00
Khaoula Bidani
edac88658e dts: arm: st: u3: add adc node in dtsi file
all stm32u3 boards have only one and same
adc peripheral.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-19 22:27:35 -07:00
Fabrice DJIATSA
4866cfcc9d dts: arm: st: l5: update dtsi file with fdcan node
add FDCAN1 node in l5 dtsi file.

stm32l5 have same ip with stm32u5.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2025-06-19 14:02:07 +02:00
Fabrice DJIATSA
67c628d025 dts: arm: st: l5: add stm32l552xc dtsi file
This dts include file is for certain stm32 boards
such as the stm32l552zc,which have a memory size
of 256KB for both flash and RAM peripherals.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2025-06-19 14:02:07 +02:00
Khaoula Bidani
20d4ab149e dts: arm: st: u3: add dac node in dtsi file
all stm32u3 boards have only one and same
dac peripheral.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-19 13:57:36 +02:00
Pieter De Gendt
a540ee6143 drivers: hdlc_rcp_if: Add HDLC SPI adapter driver
Implement the HDLC over SPI adapter driver to support the Openthread RCP
with SPI communication.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-06-18 17:50:31 -04:00
cyliang tw
bf86f1f1c0 drivers: watchdog: support numaker m55m1x
Modify driver code to support m55m1x series.
Update m55m1x.dtsi, to add wdt node for wdt driver support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2025-06-18 09:29:20 -04:00
Hou Zhiqiang
2efe6ab3bf dts: arm64: nxp: add LPI2C DT nodes for imx91
Add device-tree nodes for LPI2C instance 1 ~ 8.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2025-06-18 09:12:38 -04:00
Camille BAUD
eb06f11a8f soc: bflb: fix bl60x using wrong mtime freq
use new timebase-frequency to fix the timebase of this SoC

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-18 09:12:26 -04:00
Robert Hancock
ba2f6f8945 edac: shell: Make more generic
The EDAC shell code previously contained a number of references to the
Intel IBECC driver. Make the shell code more generic to the defined EDAC
API, and make IBECC-specific code dependent on its config option.

Also make NMI control dependent on X86 as it is specific to that
platform.

Rather than looking for a node labeled "ibecc", the EDAC shell code
now simply requires that a chosen entry for "zephyr,edac" be present to
point to the desired device. The Intel Elkhart Lake DTS has been updated
to add this alias.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2025-06-18 09:09:40 -04:00
Robert Hancock
5ec82573ca drivers: edac: Add Synopsys EDAC driver
Add an EDAC driver for the Synopsys DDR memory controller, used in the
Xilinx MPSoC (ZynqMP) devices, to allow monitoring for ECC errors.

Note that currently only the compatible string used for the ZynqMP
(shared with Linux) is currently supported. Support for other Synopsys
core implementations can be added in the future.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2025-06-18 09:09:40 -04:00
Fin Maaß
4a468e93cd dts: treewide: fix missing use of underscores
in  #83352 a few bindings were not migrated,
fix that, as it will lead to ci fails.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-06-18 09:08:05 -04:00
Yangbo Lu
af181c5620 dts: arm: nxp_imx943_m33: add NETC ENETC support
Added NETC ENETC nodes, MDIO node, and scmi power node which will
be used to power up NETC MIX in dtsi file.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2025-06-18 07:37:24 +02:00
Swift Tian
69c14e37ac drivers: mspi: add ambiq mspi timing scan utility
The utility may be used during development stage to get
ambiq platform specific timing parameters for mspi devices.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2025-06-18 07:36:26 +02:00
Swift Tian
cc5c142535 drivers: mspi: add mspi is25xx0xx device driver
This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2025-06-18 07:36:26 +02:00