Add os_timer and counter child nodes to OSTM nodes of RZ/A2M
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add Counter driver support for Renesas RZ/A2M
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add shared code in 'dac_dacx311.c' and configuration files.
Support power mode bits via configuration.
Signed-off-by: Andreas Wolf <awolf002@gmail.com>
This reverts commit 2d17d0c613
as it introduced a failure in main which can be reproduced for example
with
```
mkdir build && cd build
cmake -GNinja -DBOARD=frdm_mcxw71/mcxw716c \
../samples/net/sockets/echo_client/
ninja
```
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix dts zephyr,sram to use sram0_ns and its reg offset so that
it does not overlap the secure ram in nrf7120dk/nrf7120/cpuapp/ns
sample.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
- Deletes virtual "nxp,cmc-reset-cause" compatible,
as it is covered by existing "nxp,cmc".
- Fixes the issue discovered during discussion in
https://github.com/zephyrproject-rtos/zephyr/issues/104464
#issuecomment-3957779329
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add devicetree to support for Renesas RZ/G3E
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
The Xplained Pro layout provide a standard 20 pin header. A board
can have one or more headers and can share pins. The extension
headers are given names EXTn where n ϵ [1…7], n is determined by
which ID pin is connected to the embedded debugger.
Signed-off-by: James Liu <James.Liu2@microchip.com>
add lptmr1 node into imx95 m7 dts which locate on Always On
domain and can continue work when whole soc enter system sleep mode
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
On MAX32 SoCs, some timer instances can use an external clock input.
This commit ensures that when the external clock is selected as the
source, its frequency is read and used correctly.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Some low-power timers (LPTMR) on MAX32 SoCs support external clock
sources. Add fixed-clock nodes to the devicetree files of such SoCs
to represent these external clock inputs.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
MAX32 timers can optionally use external input/output pins.
Enable pinctrl support in the counter driver so these pins
can be properly configured via device tree.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Renames this file to have the CPU core in the filename to align
with other files, this seemingly was missed when the other files
were renamed
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add driver for the AC057TC1 5.7-inch 7-color electrophoretic (e-ink)
display. The driver supports MIPI DBI 4-wire SPI mode and includes:
- GPIO interrupt-driven busy signal handling with semaphore-based waiting
- Deep sleep and PM device support for power management
- 4-bit per pixel (2 pixels per byte) color format with 7 color palette
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Add SAU UART devicetree node support for Renesas RA0 series SoCs
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Initial SAU UART driver support for Renesas RA0 series
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Introduce the microchip,dmac-g2-dma.yaml devicetree binding file.
Add the DMA node definition for PIC32CM-JH family devices.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add the external-clock-source boolean property to the
nordic,nrf54l-lfxo binding which allows the user to configure the
lfxo in bypass mode (uses clock input on XL1 pin rather than
driving oscillator across XL1 and XL2 pins).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add device tree include file for the Alif Ensemble E4 SoC
AE402FA0E5597LE0.
This dtsi defines resources specific to this SoC variant in
addition to the common peripheral definitions from
ensemble_common.dtsi.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add device tree include file for the Alif Ensemble E6 SoC
AE612FA0E5597LS0.
This dtsi defines resources specific to this SoC variant in
addition to the common peripheral definitions from
ensemble_common.dtsi.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Modifies 1-wire serial driver to accept configurable baud rates for
Overdrive mode.
In testing with DS2488, which are Overdrive-only, it was found that
both the baud rate and zero bit pattern needed to be adjusted for
stability. This commit allows the user to define their own baud
rates for OD mode, and modifies the zero bit in OD mode.
It is assumed that most testing has been done with standard-speed
devices, so the timings and bit patterns have not been changed or
made user-modifiable.
Signed-off-by: Glenn Andrews <andrewsglenn@meta.com>
This commit implemented nxp (Semaphores2) sema42 peripheral
based on zephyr hwspinlock device driver API.
The hardware information can be find in MCXN947 RM chapter 27.
https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Move the COP watchdog device node to be a child of the SIM node, as COP
is part of the SIM register space. This can fix the duplicate unit
address warning.
Also fix the sram0 node definition in nxp_mcxc444.dtsi by deleting and
redefining it to ensure proper memory layout.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
m0-gpios and m1-gpios are common in step-dir stepper drivers
and hence placing them in common stepper-controller.yaml along
with step-gpios and dir-gpios
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Add counter driver for timer on Silicon Labs series 2.
Tested by building and running the sample on realboard
slwrb4180b and xg24_rb4187c.
Signed-off-by: Phuc Hoang <donp172748@gmail.com>
Add the `ranges;` property to the flash@0 node to properly propagate
address translations from the parent flash-controller to child partition
nodes.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Add the watchdog peripheral node to the PSOC 4100S Max SoC devicetree.
The WDT uses the SRSSLT block at 0x40030000 with IRQ 6.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add initialization ofcritical components for the RTL87x2G
series.
Key initializations include:
- Realtek OS abstraction layer.
- Clock active mode settings.
- Power Management (PM) and dynamic voltage scaling (DVFS).
- PHY and thermal compensation modules.
- Bluetooth controller ROM initialization.
Note: A mechanism is introduced to synchronize the RAM Vector Table between
Realtek's ROM code (which writes raw ISRs) and Zephyr's interrupt
management subsystem (sw_isr_table).
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
