The imx USDHC driver previously queried the peripheral's internal card
detect signal to check card presence if no card detect method was
configured. However, some boards do not route the card detect signal and
do not work correctly with the DAT3 detection method supported by this
peripheral. As a fallback, assume the card is present in the slot but
log a warning to the user.
Fixes#42227
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the clocks that get initialized for the MCXN947
when using the LPTMR. The LPTMR allows the user to select
and Input clock, however said input clock must be
initialized before the user can select it.
Update description for clk-source in binding file.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
To prepare for supporting flexcan, can node should be
renamed to canxl to support both flexcan and canxl
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
In SoC imxrt1010, edma channel has separate interrupt entry,
not like the rest of in-tree imxrt SoC series
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Adds "vib-overdrive-mv" device tree property to configure the overdrive
clamp at initialization.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Adds support for boot time configuration of the rated voltage at
initialization via "vib-rated-mv" devicetree property.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Adds the default value for the existing properties to the device tree
and fall back on those values at initialization if necessary.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
add reset control registers information (on RCC_BUS_RSTR LTDCRST bit)
for display peripheral reset.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add power management support for Apollo3/Apollo3P SPI, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P I2C, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P UART, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add initial support for nuvoton npcm400, which is a chip
family of Satellite Management Controller(SMC).
Add ecst python scripts to append the header used by ROM Code
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Add lptmr support for ke17z, add related configuration for lptmr
driver.
Add supported CPU power states for idle, stop, partial stop 1, and
partial stop 2.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
This includes helper function for pin configuration
and a DT binding for the pinctrl DT node.
There's two important notes to be made regarding this
protocol:
* pinctrl drivers have no subsytem API to implement as opposed
to clock control drivers. Because of this (and the fact that
`pinctrl_configure_pins()` doesn't require a `struct device`
handle) the pinctrl driver consists only of a helper function,
which implements the `PINCTRL_CONFIGURE_PINS` command.
Additionally, the `scmi_protocol` structure is defined inside
the pinctrl helpers source file to avoid redundant code
(otherwise, each SCMI-based pinctrl driver would have to define
it its source file).
* each vendor may have their own set of pin propeties and DT
representations for them. Because of this, there can't be a
generic, SCMI-based pinctrl driver. As such, each vendor who
wants to use the SCMI support for pinctrl operations will have
to implement their pinctrl driver (which, to put it simply,
revolves around implemeting `pinctrl_configure_pins()`) and
make use of the pin configuration function introduced in this
commit. Moreover, this means that each vendor will have control
over the way their pin properties are encoded in the
`scmi_pinctrl_settings` structure.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This includes:
1) Source containing helper functions, each
implementing a command from the clock management
protocol.
2) A clock controller driver making use of said
helper functions and implementing the clock
subsystem API.
3) A DT binding for clock protocol node.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Introduce core support for ARM's SCMI (System Control and
Management Interface). This includes:
* shared memory (SHMEM) driver. This consists of a suite
of functions used to interact with the shared memory area.
* shared memory and doorbell-based transport layer driver.
Data is passed between platform and agent via shared
memory. Signaling is done using polling (PRE_KERNEL) and
doorbells (POST_KERNEL). This makes use of Zephyr MBOX API
(for signaling purposes) and the SHMEM driver (for polling
and data transfer).
* core driver - acts as glue between transport and protocol
layers. Provides synchronized access to transport layer
channels and channel assignment/initialization.
* infrastructure for creating SCMI protocols
This is based on ARM's SCMI Platform Design Document: DEN0056E.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
Change NuMaker M463/M467 series USBD clock source to HIRC48M.
This makes core-clock and its clock source PLL not required
to be multiple of 48MHz.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Initial support for RA6M2 SoC
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
First commit to support serial driver running on r_sci_uart for Renesas
RA devices.
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Background of this modification is to make gpio driver code
provided by Renesas vendor to be an official support for Renesas
MCU on Zephyr
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Update pinctrl driver which used for Renesas RA series with
PFS secure register
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Implements the driver for the OLED SSD1327 controller.
This driver is based on the ssd1306 driver due to their similarities.
Only the SPI control bus is supported.
Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
This commit add the description of the fmc in the SoC stm32l5, and the
description of the screen controller st7789v in the board stm32l562e-dk.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
