The MAX32 RV32 core does not implement the fence instruction used by the
RISC-V synchronization intrinsic, so don't enable the builtin barriers for
that target.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add dtc property node on RX26T dts, and ram section for
dtc_vector_table on RX26T SoC for dtc support
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Reorganize ESP32-C6 LP SRAM into dedicated memory regions:
- ulp_shm: ULP shared memory for LP core communication
- ipc_shm: IPC shared memory for mbox driver
- lp_rtc: RTC data section for deep sleep persistence
- retainedmem: retained memory region with zephyr,retained-ram
Reduce main LP SRAM from 16K to 15K to accommodate the new
dedicated regions in upper LP SRAM. Update mbox overlay
references from shmlp to ipc_shm nodelabel.
Remove deep_sleep and retained_mem board overlays that are no
longer needed with the updated base DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Added support for the low side power switch pin used for switching
DUTs attached to the ADC. The switch is configured though the
drivers device tree.
Signed-off-by: Noah Stephens <nstephens78@gmail.com>
The cva6.dtsi contains bad reg values for eth and gpio peripherals.
The form reg=<0x0 base 0x0 size> has been replaced with expected
reg=<base size>.
Signed-off-by: Egon Carusi <egon.carusi@swhard.it>
Relocate common pinctrl setup to the SoC level so it can be
reused by multiple boards and kept consistent.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
- Update low power state exit latency to match SDK
- Enable NBU wakeup source
- Configure 32MHz crystal osc
- Shutdown NBU when it's not used
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Add dts support for Renesas RA8E1 SoC series
Signed-off-by: Thinh Le Cong <thinh.le.xr@bp.renesas.com>
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
stepper-ctrl is used as suffix for motion control drivers
stepper-driver is used as suffix for stepper drivers in mfd devices
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Add initial support for Analog Devices ADE7978 isolated energy
metering IC for polyphase shunt meters.
The driver implements the Zephyr sensor API and provides:
- SPI communication (read/write 8/16/32-bit registers)
- Phase A RMS current measurement (SENSOR_CHAN_CURRENT)
- Phase A RMS voltage measurement (SENSOR_CHAN_VOLTAGE)
- Device Tree bindings
This is an initial minimal working implementation. Future enhancements
will include:
- Multi-phase support (Phase B, C, Neutral)
- Active and reactive power measurement
- Interrupt support
- Calibration API
Signed-off-by: Filip Stojanovic <filipembedded@gmail.com>
Some PRs may have not been rebased to be validated using the new
dts-linter that endoced the hex values in lower case. This commit
formats the hex values in lower case for consistency.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
These are the changes generated when using the new dts-linter
All expression are now aligned with the group they are in.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
These are the changes generated when using the new dts-linter
All expression are now aligned with the group they are in.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
Remove default behavior from common zephyr,cellular-modem-device.yaml.
This allows DTS binding files to include it without "property-blacklist".
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Some modems enter a power-up sequence if reset line is held active,
so we need a way to alter the GPIO behavior.
Define a "zephyr,mdm-reset-behavior" enum in device tree to allow
choosing one, or all of the supported behaviors
* hold_on_suspend
* toggle_on_resume
* toggle_on_recovery
By default, all of the behaviors are enabled, so it matches the
previous implementation.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
The sleeptimer is mainly SYSRTC so BURTC isn't used.
Switching the defualt compatible so BURTC will be used as counter.
Signed-off-by: Shontal Biton <shontal1005@gmail.com>
Add a watchdog timer driver for all Bouffalo Lab SoC families.
Tested on Sipeed M0Sense (BL702) with tests/drivers/watchdog/wdt_basic_api.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add boolean devicetree property for setting the voltage configuration for
the nWKRQ pin GPO buffer.
The property name was chosen to match the one used in the Linux devicetree
binding.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This PR adds support for W6100 spi ethernet controller.
This driver is tested on the w6100-evb-pico
https://docs.wiznet.io/Product/Chip/Ethernet/W6100
Signed-off-by: Sayed Naser Moravej <seyednasermoravej@gmail.com>
While there was a small related piece of code in the driver,
it is not handled in the code.
Remove the related code and make clear in the binding that this property
is not supported.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
- Change the dtsi to include only r5f0_0
- Add main_rti0 and main_rti1 for a53 cores
- Add main_rti8 through main_rti11 for respective r5 cores
- Use main_rti8 for the r5f0_0 core
- Add mcu_rti0 for the m4 core
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
Now that everything uses the generic STM32L4 PLL binding, remove all
references from the the old PLLSAI binding:
- Remove the lines using div_divr (it is now post_div_r)
- Remove the clock source check since it is now done in the driver
- Remove the PLLSAI binding since it is no longer used
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Update STM32L4 PLL clock binding so that it can be used for all PLLs of
L4 and L5 series, removing the need for a specific PLLSAI binding.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Enable the SAR ADC peripheral on CY8CKIT-041S-MAX and
CY8CPROTO-041TP boards:
- Add ADC node to psoc4100smax.dtsi (SAR v2) and psoc4100tp.dtsi (SAR v3)
- Configure infineon,version property (2 for SMAX, 3 for TP)
- Configure clk-dst for peripheral clock routing
- 041S-MAX: PCLK_PASS0_CLOCK_SAR (0x12)
- 041TP: PCLK_PASS0_CLOCK_SAR (0xc)
- Reference peri_clk_div4 for ADC clock source
- Enable peri_clk_div4 in board common devicetree includes
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Add driver for the Infineon SAR ADC peripheral with device tree
binding. The driver uses a generic compatible (infineon,sar-adc)
with an infineon,version property to differentiate IP block
revisions (v2, v3). Features include:
- Single-ended and differential channel configuration
- Configurable resolution (8-12 bits)
- Multiple voltage reference sources (internal, VDDA, VDDA/2, external)
- Channel reference validation against block-level vref-src
- Hardware compensation for SAR v2/v3 single-ended channel limitation
- Interrupt-driven conversion completion
- Integration with peripheral clock control
The driver includes a compile-time per-instance API structure to
correctly report reference voltage to the ADC framework for accurate
raw-to-millivolts conversion.
Tested on CY8CKIT-041S-MAX (SAR v2) and CY8CPROTO-041TP (SAR v3) boards.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Initial generic driver for SPI-NAND devices that expose the ONFI
parameter page. Does not support advanced features such as continuous
reads, software ECC, or optional power down modes.
Configuration comes from devicetree in order to support other modules,
but is validated against the loaded ONFI data at boot.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The RV32 core does not implement RISC-V mtime, so add a new system
timer driver uses a peripheral timer for this functionality.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Moves some max32 devicetrees from arm to vendor to allow using them on
non-arm targets. This will make it possible to add support for the
secondary risc-v core that exists on these max32 variants.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
integrate the mdio driver area into the
ethernet driver area. mdio itself is defined as part
of the ethernet specification.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
