Add `pa-max-power-dbm` property to Devicetree radio node.
Set the property to the appropriate value on all Series 2 SoCs.
Add additional options for 2.4 and sub-GHz PAs.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This PR adds a new driver for the QEMU Firmware Configuration Device.
It implements the device for both X86 and MMIO architectures (e.g. ARM).
It also supports the DMA interface for write support.
Signed-off-by: Maximilian Zimmermann <gitmz@posteo.de>
Add PM support for nrf92 series products
by making power management implementation common
to all Haltium platform
Signed-off-by: Pasi Liimatainen <pasi.liimatainen@nordicsemi.no>
Basic support for GlobalTop PA6H GNSS module.
API added: set_fix_rate, get_fix_rate, set_enabled_systems,
and get_enabled_systems.
Signed-off-by: Hong Nguyen <hong.nguyen.k54@gmail.com>
sipeed vendor name had non-breaking spaces in it, which is probably not
desirable in such a low-level, very much text-only, file. Replaced with
normal whitespace characters.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Extends the PSOC 4100S MAX support by configuring TCPWM
hardware interrupts and indexes.
- Defined interrupts (mapping to IRQs 17-24) and priorities for all
eight TCPWM instances (tcpwm0_0 to tcpwm0_7) in psoc4100smax.dtsi.
- Add the 'index' property to TCPWM nodes to explicitly define
their hardware instance number
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Update bindings to consume a NVMEM cell instead of raw addresses, and
update the driver to support obtaining calibration data using the NVMEM
subsystem. For backwards compatibility and reduced footprint, the old
mechanism (direct MMIO read) is retained; a Kconfig option is introduced
to allow selecting which mechanism is used.
The sensor binding and SoC DTSI is updated accordingly.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Update bindings to consume a NVMEM cell instead of raw addresses, and
update the driver to support obtaining calibration data using the NVMEM
subsystem. For backwards compatibility and reduced footprint, the old
mechanism (direct MMIO read) is retained; a Kconfig option is introduced
to allow selecting which mechanism is used.
The sensor binding and SoC DTSI is updated accordingly.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add NVM OTP regions in DTSI of all STM32 SoCs: one region containing
calibration & other similar data, and (sometimes) another that can be
programmed in the field.
The temperature sensor and VREFINT calibration parameters are also added as
NVMEM cells in anticipation of a driver rework.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Introduce a new binding for area(s) inside Non-Volatile Memory of STM32
SoCs which can behave like OTP (i.e., can only be programmed once).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
- Get unit number and memory size from devicetree
- Renesas RZ/T2L uses at25sf128a flash chip which differs from RZ/T2M
and RZ/N2L supported previously. The Write Status Command may write
incorrect data to Status Register or Configuration Register on this
chip. Remove this code to make the driver common for other SoCs.
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add binding for the Timing Adapter and document common tuning.
This lets platforms describe TAs in Devicetree to model memory timing
for inference.
Signed-off-by: Johan Alfvén <johan.alfven@arm.com>
Add devicetree binding for the RISC-V Advanced Platform-Level
Interrupt Controller (APLIC). Uses a single compatible "riscv,aplic"
with an optional msi-parent property: when present the driver operates
in MSI delivery mode, when absent direct delivery mode is assumed.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Add CAN FD support for MCXW71 and MCXW72, where FlexCAN has been
supported but CAN FD feature has not been supported yet.
Signed-off-by: William Tang <william.tang@nxp.com>
Add CAN FD support for MCXE31x, where FlexCAN has been supported
but CAN FD feature has not been supported yet.
Signed-off-by: William Tang <william.tang@nxp.com>
Add CAN FD support for MCXA156, where FlexCAN has been supported
but CAN FD feature has not been supported yet.
Signed-off-by: William Tang <william.tang@nxp.com>
- Fix lp_gpio Kconfig dependency to use proper
DT_HAS_ESPRESSIF_ESP32_LPGPIO_ENABLED symbol instead of
SOC_ESP32C6_LPCORE, and separate GPIO_ESP32 from LPGPIO_ESP32
- fix lp_gpio compatible string to espressif,esp32-lpgpio to
match the corrected Kconfig dependency
- enable global LP core interrupts at startup via
ulp_lp_core_intr_enable() in lp_core_startup(); the LP core
has no interrupt allocator so this must be done once for any
peripheral using the single interrupt vector
- enable lp_gpio in gpio_wakeup sample overlay
- fix ESP_CONSOLE_UART_NUM default for LP HP UART console
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extends the PSoC 4100T Plus support by adding PWM pinmux definitions
and configuring TCPWM hardware interrupts.
Changes:
- Added comprehensive PWM and complementary PWM pinmux mappings in
psoc4100tp.64-tqfp.dtsi for the 64-TQFP package.
- Defined interrupts (mapping to IRQs 16-21) and priorities for all
six TCPWM instances (tcpwm0_0 to tcpwm0_5) in psoc4100tp.dtsi.
- Add the 'index' property to TCPWM nodes to explicitly define
their hardware instance number
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
- Add an explicit 'index' property to the TCPWM binding to
represent the hardware index of the TCPWM peripheral.
- This makes the configuration explicit and independent of
Devicetree node ordering.
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Some newer XIAO boards provide additional signals on the bottom side via
testing pads. This adds the new corresponding 'seeed-xioa-pads.yaml' DTS
binding for new nexus node.
Signed-off-by: Stephan Linz <linz@li-pro.net>
This commit add phy driver support for Maxlinear GPY111. This driver
implements vendor specific behaviour rgmii delay time setup, which is
not present in the generic MII driver.
Signed-off-by: Nhat Ta <nhat-minh.ta.yn@bp.renesas.com>
This adds a DAI driver for USB Audio Offload Link (UAOL)
individual streams on Intel ACE2.0 and ACE3.0 platforms.
Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
This adds a driver for USB Audio Offload Link (UAOL) IP
on Intel ACE2.0 and ACE3.0 platforms.
Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Support gathering multiple message buffers into a single write
transaction, and scattering read data from a single transaction
to multiple message buffers.
This is required for the i2c_burst_write() API to function as
expected.
The implementation uses a driver-internal buffer whose size is
configurable through the `zephyr,concat-buf-size` devicetree
property for similarity with other I2C drivers in the tree.
Gather write is implemented for both interrupt and DMA based
transfers, while scatter read is only implemented for interrupt
based transfers at this time. In the future, DMA based gather
write should be delegated to the DMA engine to perform
autonomously without needing a temporary buffer.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Consistently make use of silabs,series2-hwinfo compatible in
Series 2 .dtsi files. The compatible is not directly used to
select the hwinfo driver, but change it for consistency.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Since the system node has not been used for a long time,
it should be removed to allow other peripheral nodes to define
the register without being child nodes of the system node.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
According to NXP AN12949 (2.1.2) and UM11295 (2.1.5/10.1), the size of
the Protected Flash Region (PFR) is 12 KB, located at 0x3d000 to 0x3ffff,
and included in all LPC55S1x/LPC551x devices.
The common DTS include file for all LPC55S1x/LPC551x devices is intended
to provide the maximum flash memory configuration for 256 KB devices and
can therefore only allocate 244 KB for customer-usable flash memory. The
PFR must be 12 KB in size and bound to address 0x3d000.
Signed-off-by: Stephan Linz <linz@li-pro.net>
This PR allows to use the VOL/MICDET pin to control the DAC volume.
See chapter 6.3.10.3 Volume Control Pin of the datasheet.
Signed-off-by: Stefan Schmidt <kontakt@stefanschmidt-embedded.de>
