Add missing div-p division factor for pll clock and
respective tests in test/clock_control/stm32_clock_configuration
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Clocks are requested automatically by hardware on the nRF54H.
Remove additional handling from device drivers, and disable
the now unmanaged clocks in the devicetree.
Updates:
- can_nrf
- counter_nrfx_timer
- uart_nrfx_uarte
- spi_nrfx_spim
- spi_nrfx_spis
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The gpio pad groups are redundant if pin retention is handled per
pin, and the quirky cross domain feature is managed by the
application. Remove it entirely.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
All devices used in their "normal"/intended configuration do not
require management of the power domains, as the hardware itself will
request them automatically. Thus by default, don't specify the
power domains to avoid redundant resume/suspend cycles, which are
slow and require threading (IPC) making devices not isr ok.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Initial DMA support. DMA supports implementation of SSI IP but using vendor
specific DMA in the wrapper. The setup of the DMA is done in
mspi_dw_vendor_specific.h.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
MSPI slave mode is selected through devicetree using the
op-mode property. Mode selected by SSIISMST bit in the
CTRLR0 register. EXMIF can only be Master (controller).
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
enum mspi_op_mode in mspi.h has different syntax to this binding.
Aligning these will allow for cleaner code in the implmented drivers.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
The nrf-qspi-v2 peripheral is similar to EXMIF on nrf54h20
but supports DMA and slave-mode. The wrapper around
the SSI IP is also different with DMA features.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Add property for selecting the source for GMAC Reference Clock to dts
bindings yaml file.
Choose the source for the GMAC Reference Clock by GMAC_UR register.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add Himax HM01B0 camera sensor driver.
It depends on I2C and it is required to configure the camera.
Signed-off-by: Antonino Scarpaci <antonino.scarpaci@gmail.com>
Add device tree binding for TitanMicro TM1637 7-segment LED
display controller. The TM1637 uses a GPIO bit-banging protocol
with clock and data pins.
Properties:
- clk-gpios: Clock GPIO pin
- dio-gpios: Data I/O GPIO pin
- bit-delay-us: Bit delay for GPIO protocol timing
Signed-off-by: Siratul Islam <sirat4757@gmail.com>
- Add support Renesas r7ka8d2kflcac SoC.
- Move sdram-controller node from r7ka8p1kflcac.dtsi to ra8x2.dtsi
since this device node is available for all RA8x2 SoCs
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Fix the GPIO port "ngpios" for RA8x2 series SoCs to match
the values specified in the Hardware User’s Manual (HUM).
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
- add driver for Vishay VEML6046 RGBIR color sensor
- add new compatible "vishay,veml6046"
- support fetch and get sensor subsystem operations
- triggered mode and interrupts are not yet supported
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
- Removal of double enum (by me) caused wrong later enum entries
- See commit 36abe5efecbc27963189880d7c426c50760bcd58
- Added the second power down state (but with different name)
-> This restores the old function but still fixes the double enum issue
- The second power down state equals a different valid value
in the mode register. Documentation does not state if they
are equal but it is likely that they only differ in readback value.
-> With this change all possible register values are mapped
-> The power down state values are 0b000 and 0b100
Signed-off-by: Martin Koehler <koehler@metratec.com>
One-shot reads through Read-Decode API matches functionality
from Fetch-Get API, but asynchronously.
Streaming mode supporting FIFO Watermark Interrupts. Works for both
Gyro and Accel drivers.
These changes are covered under the build-all test for sensor async
api.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
adds the `zephyr,memory-attr` property to the SRAM1 and SRAM2
memory nodes to explicitly define their MPU attributes as normal
RAM. This ensures proper memory protection and caching behavior
when these regions are used by the kernel or application.
Resolve a Data Access Violation encountered during
test, where the faulting address was 0x30000000.
Note: add the zephyr,memory-attr property in the board overlay for SRAM2
to avoid conflict with the support of h7rs ethernet with MPU regions
enabled.
see link below for more details :
https://github.com/zephyrproject-rtos/zephyr/pull/97364/files#r2439668915
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Different Series 2 devices have different RTC IPs, despite sharing
a HAL driver. Introduce separate bindings for the different IPs, and
use a chosen node to select the node to use for timekeeping.
A chosen node was selected over a nodelabel since chosen nodes can
be overridden by board-level dts and devicetree overlays, while
nodelabels can't.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
- Add DTS for MAX32664C
- Add driver for MAX32664C
- Add example for MAX32664C Heart rate measurement with Bluetooth
- Add private attributes and channels for health measurement
Closes: #93473
Signed-off-by: Daniel Kampert <DanielKampert@kampis-elektroecke.de>
- Generate a full devices device tree file
- Use specific_part.dtsi + full_devices.dtsi way to
desribe all devices
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- add clock_init function to initialize clock sources according
devicetree settings
- finish basic clock api function
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
1. Enable MICFIL on frdm_mcxn236 board.
2. MICFIL CLOCK and DATA Pins are conflict with
flexcomm0_lpuart pins, so change flexcomm0_lpuart
pins to 'FC0_P2_PIO0_6' and 'FC0_P3_PIO0_7'.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Correct #address-cells property in exti interrupt controller nodes
for STM32 SoCs that defined it to 1 whereas value 0 is more applicable
as that interrupt does not expect sub-node nor interrupt mapping.
No functional changes as the value is ignored. This change rather targets
STM32 SoCs DTSI files consistency.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add missing #address-cells property in exti interrupt controller node.
This change prevents build warning messages when using DTC v1.6.1. With
former or later DTC versions, missing #address-cells property is ignored
but it remains requires as per DT schemas, e.g. [1]
Link: https://github.com/devicetree-org/dt-schema/blob/v2025.08/dtschema/schemas/interrupt-controller.yaml#L18 [1]
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add missing #address-cells property in exti interrupt controller node.
This change prevents build warning messages when using DTC v1.6.1. With
former or later DTC versions, missing #address-cells property is ignored
but it remains requires as per DT schemas, e.g. [1]
Link: https://github.com/devicetree-org/dt-schema/blob/v2025.08/dtschema/schemas/interrupt-controller.yaml#L18 [1]
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add SPI driver support for Renesas RZN2L, T2M
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
