Implementation of the Bosch M_CAN IP driver.
This driver is just the base for a specific SoC implementation.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Added support for GPIO driver for Intel Elkhart Lake
board.
The GPIO driver will support pin value read/write operations,
pin direction and interrupt configuration. ACPI enumeration
support and support for different GPIO communities is also
present.
Verified on ehl_crb.
Signed-off-by: U Divya <u.divya@intel.com>
ADC emulator is designed to be used in tests on native_posix board. It
supports 1-16 bit resolution range and all GAINs from enum adc_gain.
Reference voltages and number of emulated channels are set through dts.
Using special API from drivers/adc/adc_emul.h it is possible to set
constant voltage value returned by given ADC channel or set custom
function which allows to simulate complex output.
Also reference voltages can be changed in runtime using the API.
The CL also includes:
- Add adc definitions of ADC emulator in
tests/drivers/adc/adc_api/src/test_adc.c for supporting test suites.
- Add test for ADC emulator API in tests/drivers/adc/adc_emul/
Signed-off-by: Tomasz Michalec <tm@semihalf.com>
add dts bingings for dma usage
add dts support for adc with edma and hwtrigger
add a periodic_trigger feature to dts
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Add SCIF bus initial support to Renesas R-Car SOC series.
SCIF1 is used as main serial and shell output on R-Car H3 board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas has Serial Communication Interface with
FIFO (SCIF) hardware block which allow asynchronous and
synchronous serial communication. The SCIF has 16-stage FIFO
buffers separately for transmissions and reception.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Commit 233149eec5 moved flash sram nodes
under /soc for various nordic ICs, but the indentation isn't right for
52811. Fix it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Recently WiFi ESP32 driver (utilizing WiFi radio in ESP32 SoC) was
introduced into drivers/wifi/esp32/ and it already caused confusion as
there was existing drivers/wifi/esp/ directory for ESP-AT
driver (utilizing external WiFi chip, by communicating using AT commands
from any serial capable platform). So question has arisen whether it is
good to merge both, while they are totally different drivers.
Rename ESP-AT driver to be placed in drivers/wifi/esp_at/, so that it is
easier to figure out difference between "esp32" and "esp_at" just by
looking at driver name. Rename also DT compatible and all Kconfig
options for the same reason.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Remove reset pin requirement from devicetree as this
is not required for modem functionality, and is not
used in the driver anyways.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
For dmamux nodes the dma-requests property specifies the number of
peripheral request inputs(not nr. of request trigger inputs).
This commit fixes this for g4 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The MAX17262 is an ultra-low power fuel-gauge IC which implements the
Maxim ModelGauge m5 algorithm. The IC monitors a single-cell battery
pack and supports internal current sensing for up to 3.1A pulse
current. The IC provides best performance for batteries with 100mAhr
to 6Ahr capacity.
Signed-off-by: Matija Tudan <mtudan@mobilisis.hr>
reg value should match value provided within node name (as in pll@2).
Fix this to avoid warning.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add pinctrl-0 as being required on NXP Kinetis DTS bindings for I2C,
FTM, UART, and DSPI related devices.
Other devices like ethernet and CAN are utilized outside of just the
Kinetis family and thus we can not require pinctrl-0 property for them
at this time.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As the KW2XD is a SiP (System-in-package) the SPI1 controller on the MCU
is connected to the modem. As the pinctrl details for this in the
SoC dtsi file as these pins are not exposed in the pindata XMLs from
NXP.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Set SPI0 controller to default to being disabled in SoC dtsi files and
having the board dtsi files enable it. The only board that wasn't doing
this already was the frdm_kw41z.dts.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add specific binding for stm32f100 pll which differs from existing
stm32f1 and stm32f105 specific pll binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Automatic collision detection for half-duplex mode can be enabled
by setting `collision-detection` proprety for uart hardware
in the dts file. If the transmitted bit does not match the received
bit an error is raised. This is useful in RS-485 half-duplex mode.
Signed-off-by: Arvin Farahmand <arvinf@ip-logix.com>
Add binding fro stm32wl-rcc.yaml that derivates from stm32wb-rcc.
Additionally update stm32wb-pll-clock.yaml to be used as well
for stm32wl series and add missing div-m property.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks node and clocks to stm32l5 series.
PLL binding is reused from stm32l4 series.
Matching binding is updated to document that.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks nodes for F0/F3/G0/G4 series.
For F0 and G0 series, update compatible for rcc node
to specify use of dedicated "st,stm32f0-rcc" compatible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add bindings for F0/F3/G0/G4 clocks.
Introduce new rcc binding "st,stm32f0-rcc" binding
that describes RCC hardware blocks that don't have
"apb2-prescaler".
This binding also applies to G0.
Binding "st,stm32f0-pll-clock" is used for both F0
and F3 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add PLL bindings for STM32F1 devices.
- Main PLL binding for STM32F1 non connectivity lines
- Main and PLL2 binding for Connectivity lines (F105/F107)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove default pll settings to ensure pll users are correctly
configuring all prescalers on purpose and avoid surprises.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds flash clock settings in device tree for stm32h7
series such that the stm32h7 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The current serial driver uses hard code configuration. Rework driver
to use pinctrl and enable full configuration from device tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
