The BCM2711 SoC exposes 58 GPIOs. The first 28 (bank 0) are accessible
to users via the 40-pin header, while the others (bank 1) are used for
controlling on-board peripherals.
This also update doc of `rpi_4b` board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
No reason to declare it per node, as it is almostly shared by all
peripherals.
Also introduced `DT_FREQ_M` macro for better readability.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
This files has been changed as part of a refactoring in 13a87081b9.
Unfortunately the refactoring introduced few issues:
- usage of devicetree macros before their definition
- usage of pinctrl label before the definition of the corresponding node
- removal of few node overrides that are causing build errors
Unfortunately there's no board usptream using this specific dts file, so
the issue has not been caught in CI and was only found downstream.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds the RTC device to the following
atmel sam devicetrees:
- sam3x.dtsi
- sam4e.dtsi
- sam4s.dtsi
- same70.dtsi
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Enable driver for intel lw uart.
Changes from review:
- refactor spinlock to inside of loop
- use menuconfig for kconfig
- add CONFIG_UART_INTEL_LW_AUTO_LINE_CTRL_POLL
Signed-off-by: Teoh Shi Lin <shi.lin.teoh@intel.com>
add basic sensor support for 3-axis accelerometer, currently
this driver support data acquisition and motion detection
features.
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
HAS_DTS has become a redundant option. All Zephyr architectures now
select this option, meaning devicetree has become a de-facto
requirement. In fact, if any board does not provide a devicetree
source, the build system uses an empty stub, meaning the devicetree
machinery always runs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
STM32WB MCUs has two AES peripeherals. Add AES1 definition, AES2 must not
be used by application CPU core.
Signed-off-by: Lukasz Hawrylko <lukasz@hawrylko.pl>
Add wakeup_duration support. (WAKE_DUR in WAKE_UP_DUR)
Value is configurable through DT per instance.
Signed-off-by: Adrian Wojak <adrian.wojak@outlook.com>
Use a new property, "clock-mux" to select the clock mux for the SAI.
Previously, the clock mux was being selected using the "bits" specifier
of the "clocks" phandle property, which is not the purpose of this
specifier. This can be shown by the regression introduced by 5bebbb91,
which changed the "bits" field to the clock gate shift (which is the
intended meaning).
This incidently worked for the SAI1 and SAI3 peripherals, as the lower 2
bits of the correct clock source selection (0b10) are the same as the new
value placed in the "bit" specifier. For SAI2, the clock source was
switched to PLL3 PDF0 by this change.
To resolve this, use an explict "clock-mux" property for this selection.
Fixes#63541
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a new SPI shim driver for Intel SoCs. Builds upon the SEDI bare
metal SPI driver in the hal-intel module.
Co-Authored-By: Kong Li <li.kong@intel.com>
Signed-off-by: Ye Weize <weize.ye@intel.com>
Adds a devicetree for describing common battery characteristics used
by multiple devices and subsystems.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
MEC172X series SoCs share most IP but the -LJ series expands the PWM and
ADC channels available as well as defines extra pinctrl pins.
Separating these better to be able to simplify their inclusion and
driver code. Any board based on either the -SZ or -LJ package can just
include the mec172x<sz/lj> dtsi files for their specific package.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
This is needed since commit f66b73197d
("drivers: hwspinlock: implement sqn hwspinlock driver") started
using it. Not sure how this got past CI.
Signed-off-by: Martí Bolívar <mbolivar@amperecomputing.com>
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;
- added bias_high_impedance option
- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Define WKPU interrupt controller node and its respective interrupt
sources mapping to GPIO pins.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Extend the NXP S32 GPIO driver to be able to route external interrupts
to either SIUL2 EIRQ interrupt controller or, when available on the
SoC, WKPU interrupt controller.
Since WKPU can support up to 64 external interrupt sources and SIUL2
EIRQ up to 32, gpio_get_pending_int() is removed and the interrupt
controller specific API must be used instead.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce an interrupt controller for the NXP S32 WKPU peripheral
that can be integrated with GPIO to trigger interrupts through
external interrupt pad inputs.
WKPU can trigger interrupts from certain input pads that support this
function, as well as wake-up events to the power management domain. This
patch only adds WKPU functionality as an interrupt controller to extend
the number of input pads that can interrupt the core. Power management
functionalities are not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The example sets the power-role to "SINK", but the value is
case-sensitive and only accepts lowercase "sink".
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
Specify only the bus corresponding to the current yaml file, as done in
the adi,adxl372-spi.yaml.
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
The PCA9633 i2c LED controller offers an All Call address in its nominal
operation, allowing simultaneous communication with all instances present
on the same i2c bus. The default address is 0x70. While this functionality
is convenient, it is possible that the board uses another i2c component
that also uses this address (for example, the shtcx). In such cases, the
address conflict prevents the proper functioning of the system.
The idea is to add a "disable-allcall" property to the device tree. If this
option is present, the initialization of the PCA9633 forces the bit 0
(ALLCALL) to be set to false, thereby disabling this function. It is
necessary to add this property to all PCA9633 devices on the bus to free up
the address 0x70.
Signed-off-by: Steve Jacot-Guillarmod <steve@piziwate.net>
Increase the `ndev` of PLIC to the max of 1024 from 53, as
supported by the RISCV PLIC. The total number of IRQs is now
1035(1024 + 11), up from 64(53 + 11).
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The pre-alloacted size of the buffer for the SHA ROM API code increases
in npcx4 chip. This commit adds a new property context-buffer-size to
sha0 DT node in npcx9 and npcx4 separately. The driver can pre-allocate
buffer with the correct size based on the property.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Different nRF52 devices have different maximum TWI DMA transfer size,
and it's easy to hit the limit with i2c displays on nrf52832 (8 bit) and
nrf52810 (10 bit). Currently neither the driver or the hal validate the
limit, leading to random NACK errors when trying to transfer more data.
Add a check on the driver to fail gracefully when going over the limit.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
These two have been converted from kscan to input already, move the
bindings over to match the change.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reword the descriptions for the bus-speed, sample-point, bus-speed-data,
and sample-point-data CAN controller devicetree properties.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.
Updated devicetrees that has PLIC accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Removing the edge-trigger Kconfig as it is supported by default
in the RISCV PLIC specifications.
Define the edge-trigger register offset in the driver instead
of retrieving the value from devicetree as it is not something
configurable. The value 0x1080 is defined in Andes & Telink
datasheets.
Updated build_all testcase.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Added pinctrl nodes for Silabs SoCs where they were missing:
efm32pg, efm32hg, efm32wg, efr32mg21.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
This continue PR #31270. The updated changes are:
- Updated to work with latest zephyr
- Inplace reads/writes of registers
- Batch read of RX messages when multiple messages can be read
- FIFO abstraction of RX/TEF queues
- Handle ivmif errors
- Use READ_CRC for register reads
- Use bitmasks instead of bitfield members
- Rename mcp25xxfd to mcp251xfd
- General cleanups
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
