Add a function that uses the JESD216 SFDP BFP DW16 Enter 4-Byte
Addressing parameter to put the device into 4-byte addressing mode if
one of the entry modes that's supported by the driver is available on
the device.
Perform the transition if SFDP data is provided (either by devicetree
or at runtime), or if a special devicetree property provides the entry
mode descriptor.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Provided nodes reflect the clock tree of each series.
Clock nodes are disabled by default but populated with default
start up configuration. Main reason is the we don't want to
impact boards using Kconfig based clock configuration for now.
Exception to these rules:
- syslck: Default enabled, clock frequency and clock source not
provided
- pll: clock source not provided
This is made on purpose so that errors are triggered if parameters
essential to the board configuration are not provided.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL adds a override mechanism for pwm module's input clock source
assignment. If the 'clock-bus' property exists, the NPCX_DT_PROP_ENUM_OR
macro function will return an enum upper token value. Otherwise, it
expands to default value in 'clocks' property.
For example, if the users want to select LFCLK as pwm0's input clock,
ths node can be overridden by adding 'clock-bus' property with an enum
string, "NPCX_CLOCK_BUS_LFCLK".
&pwm0 {
status = "okay";
clock-bus = "NPCX_CLOCK_BUS_LFCLK";
};
Signed-off-by: Keith Short <keithshort@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
i2s1 is not present in all stm32f4 series. So moving the i2s1 node
from the top level stm32f4 dtsi file to the stm32fxx specific dtsi
files. Also in stm32f429zi, the sequence starts from i2s2, this commit
helps in having the right channel number.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
STM32G0 is supported by the st,stm32-dma-v2 driver.
This commit adds dma1 and dmamux dts bindings
for stm32g03x, stm32g05x and stm32g07x.
For stm32g0bx additionally dma2 is added.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Exit latency is the maximum time required by a CPU to transition from
a specific idle state to active state. This information is going to be
used to properly configure the wake up event in order to the system be
able to execute the next scheduled task.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This patch adds flash clock settings in device tree for stm32wb
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32l1
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g4
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This patch adds flash clock settings in device tree for stm32g0
series so that the stm32 flash driver can get the clock settings
from this dtsi file.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.
This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
NPCX PWM supports output buffet select to push-pull or open-drain. Add
output buffer select option 'drive-open-drain' in devicetree for NPCX
PWM. If set, the PWM output will be configured as open-drain. If not
set, defaults to push-pull.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The binding-template.yaml file has grown organically into something
that's out of control.
It makes too many 'see above' and 'see below' references to be read
comfortably, and we can't cross reference from YAML.
There are also many example DTS and YAML fragments scattered about in
comments, which cannot be syntax highlighted properly.
Fix that by overhauling the documentation into bindings.rst in the DT
guide. This will let us link to individual sections when answering
questions, allows us to cross-reference and use '.. code-block::',
etc.
A couple of things need to go to other pages.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
1. add a seperate 2 cores SMP board configuration to run in Jailhouse
inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will
run on Core2 and Core3.
2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in
dts/arm64/nxp/ directory.
3. Add myself to be code owner of directory dts/arm64/nxp/.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Enabling pwm on timer3 for stm32l1 series in dtsi.
Adding other timer nodes for pwm capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Renesas RCar Gen3 series have up to 8 GPIOs
bank.
Add bank 5 and bank 6, that is used to manage user led and
switches on different demo board.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The Compare match timer can be found on Renesas
RCar Gen3 soc series.
It depends on clock controller to supply clock to the
CMT module.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
These changes turn out to have been incompatible with the way pinctrl
drivers are going to work, so we need to go back to what we had before
until we can agree on a better approach.
Squash of the following reverts:
Revert "boards: nrf: fix deprecated I2C properties"
This reverts commit 2a4ac9ac02.
Revert "samples: switch nrf overlays to sda-gpios, scl-gpios"
This reverts commit 01bb08e7d8.
Revert "boards: nrf: switch to sda-gpios, scl-gpios"
This reverts commit 17a66304c4.
Revert "i2c: nordic: switch to phandle arrays for pinmux"
This reverts commit 821c03a14a.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When 1.8V is disabled, sdhc can only
communicate at low speed. But this can
save the external circuit for switching
between 3.3V and 1.8V, which is very
practical in costdown scenarios.
Signed-off-by: Frank Li <lgl88911@163.com>
Enabling PWM on timer1 for STM32F2 platform in dtsi.
Adding other timers nodes for PWM capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Some SPI NOR devices, particularly Atmel and SST, power-up with block
protect bits set in the status register. These bits must be cleared
before any erase or program operation can succeed. However, blindly
clearing bits in SR is wrong as some of these are non-volatile and
control chip behavior, including quad-enable.
Add a devicetree flag to identify device-specific BP bits in the status
register that should be cleared on startup only for devices that need
them, and when set do the clear during initialization.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Define the FLASH_CCFG memory region from a devicetree partition instead
of from math in the linker file. Removing the special math case results
in the FLASH_CCFG region overlapping the FLASH region, but the linker
accepts this until the FLASH region actually starts placing variables
in the FLASH_CCFG region.
As a result, applications that don't fit in (FLASH_SIZE - 88) bytes will
still fail to link, just with an overlapping memory region error instead
of an overflow error.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Move the definition of the two IPC RAM blocks from `#define`'s in family
linker scripts to proper devicetree nodes. Use the devicetree nodes to
generate the memory regions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Currently the SRAM location is fixed for all the boards derived from
qemu_cortex_a53. While this is acceptable when the image is directly
loaded in SRAM by QEMU, in some cases Zephyr can be loaded in RAM by
another piece of software or by semihosting at a different address
before jumping into it.
When for example TF-A is used and Zephyr is run as BL33 payload using
QEMU, in this case the default location in RAM is at a different
address (when preloaded BL33 base address is not used).
To address these cases, move the SRAM location into the board-specific
DTS so that it can be adjusted on a board by board basis.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fixed the name of nodes in in espi-vw, miwu-wui, and miwu-int
device-tree node. This CL fixed missing nodes in CL d3a94fa8ab.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The following is the interrupt priority plan for ec application.
The original IRQ priority map in Chromium EC is:
- IRQ priority 0:
|-ITIM IRQ for Warning watchdog.
-IRQ priority 1:
|-UART IRQ for signle byte FIFO in npcx5 series.
(Ignore it since UART has 16 bytes FIFO in npcx7 and later series.)
-IRQ priority 2:
|-SHI IRQ for FIFO FULL and Half FULL event.
|-MIWU IRQ for SHI CS. (Wake-Up ASAP for handling data from SPI bus.)
-IRQ priority 3:
|-All MIWU IRQs for GPIO, MTC and eSPI VW events.
|-ITIM IRQ for task scheduling.
|-ITIM IRQ for time-out.
(No need in Zephyr since 64-bit timer support.)
IRQ priority 4:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
|-PECI IRQ
IRQ priority 5:
|-Keyboard RAW IRQ
|-PS2 IRQ
Then, this CL arranges the priority of npcx interrupts in Zephyr as:
IRQ priority 0:
|-Reserved it for further requirements.
IRQ priority 1:
|-SHI IRQ for FIFO FULL and Half FULL event.
| (Will modify it in ec repo.)
|-MIWU IRQ for SHI CS (Will modify it in ec repo.)
IRQ priority 2:
|-MIWU IRQ for GPIO, MTC, T0 timer and eSPI VW events.
|-ITIM IRQ for task scheduling.
IRQ priority 3:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
IRQ priority 4:
|-Keyboard RAW IRQ. (Will modify it in ec repo.)
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
For i2c-devices, reg is the address. This took me way to long to
discover and I wanted to leave a breadcrumb for the next Zephyr newbie.
Signed-off-by: Jeremy Bettis <jbettis@chromium.org>
