And removes the odd esp32c3 competible from it
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
hal_espressif repository was updated from esp-idf v4.2
to esp-idf v4.3 to allow latest Espressif chips integration.
As a consequence, it added a few changes in drivers
and peripherals. To maintain bisectability, changes in this
PR cannot be split. Here are some details:
wifi: update linker script by adding libphy and new attributes.
spi: update some APIs and fixed missing wait_idle check
west.yml: esp32: update hal to new version
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit adds max-erase-time element which holds the
maximum erase time of a sector or page or half-page for
all the series of stm32.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit defines max-erase-time element inside flash-controller
to be part of device tree.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Add the lptim1 device node definition and enable the corresponding
exti interrupt in sys_clock_driver_init().
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Move lis2dw12 trigger pulse configurations from Kconfigs to Device Tree.
Moreover the dts properties have been renamed as 'tap', which sounds a
better name to immediately catch the feature behind it. Since tap
threshold cannot be zero, this value (which is the default in dts
binding) is used to enable/disable the device feature per each axis.
The event can be generated on INT1 only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Take the int-pin information (i.e. what pin between INT1
and INT2 the drdy is attached to) directly from DT.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Create a common binding file that will be included by all bindings
handled by lis2dw12 driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add a device node for the FMC controller found in stm32f427, f437 and
f446 devices, works fine with the current memc_stm32_sdram driver.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
bits property indicates the number of in-use slots of available slots
for GPIOS. We have a similar property ngpios in gpio-controller.yaml,
we will use ngpios to calculate port_pin_mask. Let's remove bits and
only use ngpios.
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
The NXP LPC syscon driver failed to build on several platforms for
various reasons. We need dts support on LPC55s1x and LPC55s2x, the
driver doesn't seem like it will work on LPC54114 so we exclude it
there for now.
Additionally, fix a dtc warning on LPC55s6x based on unit-address in
the node naming needing to be lowercase.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.
TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
"flash read 0x80000 0x100"
"flash erase 0x80000 0x1000"
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
The atmel pwm driver doesn't have a easy way to test and show
functionality to users. This re-assign led-0 function from
gpio-leds to pwm-leds. The current led-0 entry at gpio-leds
was keep with status disabled, as refence. It allows test pwm
driver for SAM Cortex-M7 MCUs. The led-1 assume Zephyr sample
default led0 alias.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add the device tree data for the 4 Ethernet controllers integrated into
the ZynqMP SoC, GEM0 to GEM3.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add support for the Xilinx GEM Ethernet controller, which is integrated
in both the Xilinx Zynq and ZynqMP (UltraScale) SoC families. The driver
supports the management of a PHY attached to the respective GEM's MDIO
interface.
This driver was developed with ultimately the Zynq-7000 series in mind,
but at the time being, it is limited to use in conjunction with the
ZynqMP RPU (Cortex-R5) cores. The differences are minor when it comes
to the adjustment of the TX clock frequency derived from the current
link speed reported by the PHY, but for use in conjunction with the
Zynq-7000, some larger adjustments will have to be made when it comes
to the placement of the DMA memory area, as this involves the confi-
guration of the MMU in Cortex-A CPUs.
The driver was developed under the qemu_cortex_r5 target. The Marvell
88E1111 PHY simulated by QEMU is supported by the driver.
Limitations currently exist when it comes to timestamping or VLAN
support and other minor things. Those haven't been implemented yet,
although they are supported by the hardware. In order to be fully
supported by the ZynqMP APU, 64-bit DMA address descriptor format
support will be added.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit fixes the compilation warning occurred due
to usage of upper case in "interrupt-controller@4000F400".
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit adds PWM support in dtsi for stm32l5 series. Adding
other timer nodes for different stm32l5 series PWM capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Convert the keyscan portion of the Holtek HT16K33 driver to adhere to
the kscan API instead of the GPIO API.
When this driver was introduced the kscan API was not present. The
keyscan driver was therefore implemented as a GPIO interrupt driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
GPIOTE1 on the nRF5340 SoC is always accessible as a non-secure
peripheral. However, it is only defined in the non-secure DTSI file.
This is therefore a missing node in the secure DTSI file, since
non-secure addresses are accessible by secure software.
Move the node definition to a common include file and pull it into the
app core DTSI as well. To keep things clean, adjust the node labels so
that:
- 'gpiote0' and 'gpiote1' are defined in the secure DTSI
- 'gpiote0' is not defined in the non-secure DTSI
- 'gpiote' is defined in both secure and non-secure DTSIs
- 'gpiote' refers to the same node as 'gpiote0' in the secure DTSI
- 'gpiote' refers to the same node as 'gpiote1' in the non-secure DTSI
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The sram1 node in nrf5340_cpuapp.dtsi represents the SRAM accessible
to the network core on the SoC.
However, while the network core can access the app core's SRAM, the
app core cannot access the net core's SRAM. Therefore, the sram1 node
should only appear in DTSI files for the net core, and not the app
core.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The RAM of can instances starts directly after it's predecessor.
This commit fixes can2 and can3 support for stm32g4 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Property "st,prescaler" of binding "st,stm32-pwm" was set to 2
different default values 0 or 10000 in *.dtsi files.
Since this property rather depends on application than hardware
description, there is no reason to have 2 different default values
in use. Besides, it is a trap for pwm users that should take into
consideration this random default value.
Fix this by defaulting the property systematically to 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add radio peripheral to nrf5340_cpunet DTS. The peripheral
description includes antenna matrix congiuration for Direction
Finding extennsion.
Appropriate binding file for nRF radio peripheral already egxists.
There is no default antenna matrix configuration. Antennas number
and GPIOS mapping to DFEGPIOS is project specific.
Complete configuration must be provided by end user as overaly.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Clean up multi-line strings so they will show up properly in the
bindings index in the HTML documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
