1. Support USB-C drivers TCPC, PPC, and VBUS with UTCPD H/W IP
2. UTCPD is interconnected with Timer-triggered EADC for updating
VBUS/VCONN voltage periodically
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The I2C API itself now enforces last msg stop, remove duplicate code
from driver.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Remove the ‘HAS_MCUX_ACMP’ Kconfig, and also remove it from
driver and soc Kconfig files. It is not needed since we already
depend on 'ACMP' enabled in the dt file, the 'HAS_MCUX_ACMP'
kconfig is a relic of the past before devicetree was stable.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
When using the eeprom_target in 16-bit mode on rp2040, some issues in the
addressing have been observed where the read was executed before all writes
where finished.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Set the correct the phy_itface depending on the setting
Save few lines after resetting the priv->pcd structure
with the memset
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In lis2dux12_set_odr(), the call to stmemsc module lis2dux12_mode_set()
API is done with the .fs field left uninitialized, so setting the
underlying device regs in an unproper way.
Suggested-by: Luis Ubieda <luisf@croxel.com>
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In the it8xxx2 chip, the interrupt for INT0 is reserved. However,in some
stress tests, the unhandled IRQ0 issue occurs. To prevent the system from
going directly into kernel panic, we implemented a workaround by
registering interrupt number 0 and doing nothing in the IRQ0 handler.
The side effect of this solution is that when IRQ0 is triggered, it will
take some time to execute the routine. There is no need to worry about
missing interrupts because each IRQ's ISR is write-clear, and if the
status is not cleared, it will continue to trigger.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
So far receving was possible in active mode, but IP and port information
was not fetched nor propagated to application layer. Support fetching that
information even in active mode, so that using bind() with recvfrom() is
working accordingly.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This is just a step forward to make cmd_ipd_parse_hdr() capable of parsing
IP address and port when CONFIG_WIFI_ESP_AT_PASSIVE_MODE=n. After obtaining
this information (IP and port) it will be simply much easier to write this
information into 'struct esp_socket' directly, instead of passing to upper
layer.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Treat ':' similar as ',', '\r' and '\n', so that AT response parameter
parsing can be gracefully stopped.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Use it to get information about RSSI. In subsequent commits this helper
will be used to get other information as well.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
'struct sockaddr_in' should contain port number in network byte order. This
means that htons() macro should be used, instead of ntohs().
This was working before since both htons() and ntohs() end up in calling
BSWAP_16().
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This variable is only used under DUAL_BANK condition and a warning
is generated in !DUAL_BANK case, so move its definition accordingly.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
During driver init make sure that the IRQ_CTL field is set before enabling
the interrupts. Fixes the i2c read error on startup.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
When QSPI configuration is the dual-flash, the total
flash size and erase size are doubled. This is handled
with a STM32_QSPI_DOUBLE_FLASH factor which doubles
the values of one qspi component.
Note that SFDP table is for ONE flash component.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rename it from litex,eth to litex,liteeth
to reflect the new name of the driver.
Zero got removed from the litex
ethernet compatible, as it now supports
multiple instances.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
add helper for interrupts, so multiple
instances of peripherals work.
this way out-off-tree peripherals are supported.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a void *user_data pointer to the input callback structure. This is
useful for driver to get back the driver data structure and avoid
defining wrapper functions.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update in-tree device drivers to depend on the reference frame
datums they support.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add choice symbol for reference frame datum from which GNSS will
produce navigation data. All in-tree device drivers use WGS84 by
default, for now, this is the only available option until support
for other datums are added.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Moved the definition of the phy device from depending on stm32hx
series SOC to its own #if...#else...#endif. This way mdio support
can be enabled on any stm32 soc that supports it by defining the
mdio node in the devicetree.
I have tested this in a custom board.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
Driver includes wrong header zephyr/usb/usb_device.h and uses defines
from include/zephyr/drivers/usb/usb_dc.h.
Also fix udc_ep_enable() implementation in general. HAL_PCD_EP_Open()
takes the ep_type parameter as uint8_t integer type and the shim driver
should not just pass int type.
It is recommended that drivers use ep_cfg or cfg for struct
udc_ep_config, fix this as well.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The global otg interrupt hs/fs is enabled by the udc_stm32
driver. Get it in the list of interrupts of the OTG node.
Use UDC_STM32_IRQ naming.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The offset is wrong when the second bank is used by M4 as the
offset is relative to the base which is 0. So add the least
significant 6 nibbles from the CONFIG_FLASH_BASE_ADDRESS to
find the sector.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Currently flash controller driver builds and runs only on M7.
This patch supports enablement of the driver on M4 CPUs. The
main issue in using the driver on M4 is that LL_GetFlashSize()
to read the flash size works only on M7 as the internal register
is not accessible from M4. So to use the driver on M4, add a dt
property, bank2-flash-size, to configure flash size of bank2.
this will allow gradual support of flash controller driver
on M4 of all supported STMH7 boards by defining the above
dt property and testing it. Currently this is verified only
on STM32H747i-disco board.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
Remove BUILD_ASSERT for Internal DMA and DCACHE if both are enabled, and
enable Internal DMA support by default.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
UDC_BUF_POOL_*_DEFINE macro will place buffer pool in __nocache
section if NOCACHE_MEMORY is enabled.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Introduce UDC_BUF_POOL_*_DEFINE macros based on NET_BUF_POOL_*_DEFINE
macros but use our own version of alloc and unref callbacks to get
buffers with specific alignment and granularity. Also, do not use ref
callback because it breaks alignment.
Also introduces helper macros for defining and checking UDC
driver-compliant static buffers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add the missing timeout parameter to `modem_pipe_open`. 10 seconds
appears to be the default value added to other in-tree drivers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Revision 1p7 of the silicon added support for IBI TIR, full word fifo
while target usage, defining byte with direct CCCs. This also adds
support of HDR-DDR.
This also fixes short ccc commands where multiple targets in a
payload for the same ccc.
Modification of the i3c_target_tx_write had to be done in order to
distinguish the difference for each fifo to be written to.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
