Fix incorrect behavior for non-8-bit SPI word sizes.
Fix the handling when both TX and RX buffers are NULL.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Enable IOCON clocks from the devicetree clocks property during
pinctrl initialization.
Keep the existing LPC path intact and only use the clock control
flow when a clock is described in devicetree.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx IOCON clock IDs to the MCUX SYSCON clock bindings and
handle them in the shared clock control driver.
This provides the common gate support needed for RT7xx IOCON
instances to be managed through the clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Use the optional clocks property to request the GPIO port clock
during driver initialization.
This lets RT7xx GPIO instances rely on the common clock control
path instead of board-specific clock enabling.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx GPIO clock IDs to the MCUX SYSCON clock bindings and
handle them in the shared clock control driver.
This provides the common GPIO gate support needed for RT7xx
GPIO instances to be managed through the clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The RA SDHC driver handles SD_SWITCH/CMD6 through
r_sdhi_read_and_block(), then copies the returned status from the
FSP aligned buffer into the Zephyr request buffer.
CMD6 switch status is a 64-byte data block. The driver copied only
8 bytes, which is the SCR size used by ACMD51. This left byte 13
uninitialized or stale, so the SD core could read bus_speed as 0.
With bus_speed misread, the SD core skipped high-speed setup. Since
the current init flow switches to 4-bit width after high-speed setup,
ACMD6 bus-width switching was also skipped despite host and card
both advertising 4-bit support.
Copy ra_cmd.sector_size bytes instead, matching the requested data
block size. For CMD6 this preserves the full 64-byte switch status.
Signed-off-by: Shan Pen <bricle031@gmail.com>
Added autanalog CTB support for PSE84 device.
This implementation uses the autnonomous controller (MFD)
that is shared with other autanalog drivers.
The CTB stands for Continuous Time Block. It is a set of opamps
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
Each CTB block contains two opamps, which need to be configured
together and accessed using the AC. A CTB MFD is used to bring
together the two opamp configurations. AC MFD then references the
combined CTB MFD configuration, and brings together all other
autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
The missing errno return in ibi path causes the function
to return 0 (success) when raising ibi times out.
This patch addresses this issue.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
shell_info is intended for informational side-notes, not for printing
command result data. Use shell_print instead, consistent with other
Zephyr driver shell implementations (rtc_shell, gpio_shell, i2c_shell,
eeprom_shell).
Signed-off-by: Nick Ward <nix.ward@gmail.com>
Assisted-by: Claude:claude-sonnet-4-6
When the TimeOut is enabled in MemoryMapped mode, the TO irq callback
has not to give any sem, because the read operation is done with
memcopy(). No sem was taken, nothing to release.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When using a 32-bit based I2S peripheral such as a PCM1809, the default
DMA configuration of 16 bit doesn't work; due to the incorrect length,
the I2S buffers are filled with only zeroes. Rather than hardcode 16 bit
length, check for word size and set the DMA configuration accordingly.
Signed-off-by: Peter Allenspach <uberrice@pm.me>
The function lfclk_spinwait in the clock_control_nrf.c driver uses
k_cpu_atomic_idle() to idle until the CLOCK IRQ caused by the
LFCLKSTARTED event is triggered.
The implementation of the (check -> set -> idle) loop breaks if
unrelated clock events like XOSTARTED and XOTUNED occur concurrently,
since they trigger the the CLOCK IRQ as well. This can wake up the
CPU before LFCLKSTART event, which means NVIC_ClearPendingIRQ() is
not called before we enter idle again.
Solve the race condition between
(critical section -> check -> set -> maybe clear pending -> idle)
by refactoring it to
(critical section -> clear pending -> check -> set -> idle)
Which ensures the LFCLKSTARTED event is not lost if it occurs during
the (check -> set -> idle) flow.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Use LL_PWR_* APIs to handle UCPD_DBDIS flags in portable way.
Fix ucpd_params.psc_ucpdclk value.
Signed-off-by: Vladimir Zidar <vladimir.zidar@ars-es.com>
When a DMA channel is routed through the channel mux (dma_slot != 0), each
minor loop is paced by the peripheral request signal. In this case, the
caller-chosen burst length must be preserved to ensure correct operation.
Previously, the driver would collapse the minor loop into the whole block
for all memory-to-memory transfers without source chaining, but this logic
should only apply to genuine software-triggered transfers. Peripheral-
triggered transfers (e.g., FlexIO LCDIF) expect one minor loop per shifter
round, and collapsing the loop breaks this requirement.
Add a check for dma_slot == 0 to ensure burst length collapsing only occurs
for software-triggered transfers, not peripheral-triggered ones.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Nordic's nPM10 Series PMIC watchdog driver implementation and devicetree
bindings.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Add timer support to the nPM10 Series MFD driver. This can be used as a
general purpose timer, wakeup timer for hibernation modes and as watchdog.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Drain any pending bytes on the pipe when `modem_at_user_pipe_claim` is
called, as these will either be unsolicited notifications or messages
from previous users of the pipe. Draining the pipe on claim prevents
this data appearing in unexpected places.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add a timeout parameter to `modem_at_user_pipe_claim` to enable blocking
for a duration on pipe availability.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Update the AT user pipe API so that the initialisation does not require
the modem chat instance. This enables sharing the user pipe abstraction
between multiple users at runtime.
One consequence of this is that `modem_chat_attach` is deferred until
the user calls `modem_at_user_pipe_claim`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
LL_TIM_TRGO_UPDATE isn't yet implemented on STM32WB0x series.
Exclude WB0x series from using LL_TIM_TRGO_UPDATE.
This is addressed by testing HAS_MASTERMODE_SUPPORT that is disabled
for platforms not defining LL_TIM_TRGO_UPDATE.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The CRC16 reflect issue is not accepted by the Renesas RA driver,
even though it is supported by the HWIP.
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Replace direct esp_cache_msync() calls in the ESP32 GDMA and
SPI master drivers with the portable sys_cache_data_*() API.
Zephyr's API is a compile-time no-op when CACHE_MANAGEMENT is
disabled, so the same source compiles cleanly on every ESP32
SoC and stays cost-free where there is no writeback cache.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Map the generic sys_cache_data_* API onto esp_cache_msync()
from hal_espressif. The driver is SoC-agnostic and activates on
any Espressif chip that selects CPU_HAS_DCACHE and enables
CACHE_MANAGEMENT, keeping PSRAM and DMA buffers coherent from
portable Zephyr code.
Instruction-cache and enable/disable entries are no-ops since
the bootloader brings the cache up before Zephyr runs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Sets `ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK` to defaut enabled.
This guarantees that VWires sent by the target are received by the
controller before the driver API returns.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The PIN_WAIT_INTERVAL_US timeout of 2000 microseconds is
insufficient for reliable hardware response. Increase it to
10000 microseconds to match the previous driver implementation
(i2c_mchp_xec.c) which used WAIT_INTERVAL * WAIT_COUNT for an
effective 10 ms timeout.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Fix a race condition in start_next_packet() where the async timeout
timer is armed after writing the SER register (which starts the
transfer). On platforms where the bus transfer completes faster than
the CPU can execute the subsequent instructions, the ISR fires and
calls k_timer_stop() on a timer that hasn't been started yet.
The orphan timer fires after the configured timeout. At that point
the transfer context is stale: packets_done may index past the
original packets array, leading to out-of-bounds access, USAGE FAULT
(unaligned access), or BUS FAULT (dereferencing freed stack pointers).
Fix by moving k_timer_start() before write_ser(). The timer is now
armed before the transfer can possibly complete. If the ISR fires
immediately, k_timer_stop() in handle_end_of_packet() safely cancels
the already-running timer. For sync transfers the timer is not armed,
preserving the existing behavior.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Adds support for no increment needed to support the LPSPI and other
peripherals with a FIFO buffer.
Furthermore we disable interrupts on each major loop on SG, instead
only do an interrupt on the final TCD.
Also a small optimization in dma_mcux_edma_reset_channel, where TCD
got zeroed twice.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Improve the LPSPI RTIO FIFO path by increasing the fifo
watermark if possible, this reduces IRQ load. Add DMA
support
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Added PTComp support to PSE84.
This implementation uses the shared autonomous controller (MFD)
with other autanalog drivers.
The PTComp is a programmable threshold comparator inside the
autonomous (aut) analog subsystem. It is controlled using the
autonomous controller (AC), which is a programmable state machine.
The AC is shared across all autonomous analog peripherals including
the SAR, PRB, PTComp, CTB, and CTDAC.
The PTComp block contains two comparators for edge detection and
with a capability for boolean post-processing. These two comparator
instances need to be configured together and accessed using the AC.
A PTComp MFD is used to bring together the two comparator
configurations. AC MFD then references the combined PTComp MFD
configuration, and brings together all other autanalog peripherals
into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add DAC driver for the Analog Devices AD5529R 16-channel, 16-bit
voltage output DAC. The driver supports multiple output voltage
ranges, SPI communication, and optional reset/LDAC/clear GPIOs.
Signed-off-by: Robert Budai <robert.budai@analog.com>
Co-authored-by: Radu Ciobanu <raduciobanu096@gmail.com>
Replace the SDL display driver's default pixel format Kconfig
selection with a devicetree property and initialize the display
using the DT-provided format.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Drop the Espressif-specific ESP32_WIFI_STA_AUTO_DHCPV4 Kconfig and
switch the driver to the generic WIFI_STA_AUTO_DHCPV4 option added
in the Wi-Fi L2 layer. The new option provides the same behavior
across all in-tree Wi-Fi drivers, allowing applications to control
automatic DHCPv4 start uniformly regardless of the underlying SoC.
A migration note is added so applications that previously disabled
the vendor option know to disable the generic one instead.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Some peripherals e.g. some chips' GPIO ports may have their clocks
fixed to enabled and their clock module IDs are not defined. Skip these
modules when they are passed in.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
The option was deprecated without a migration path or reasoning. The PSA
interface is the only source of entropy for some setups. For example
TF-M, as the crypto hardware is on the secure side. Deprecating the
symbol while it is still enabled by default from devicetree just leads
to compiler warnings and confusion.
This reverts commit 04b003a5b1.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Follow the pattern used by other PHY drivers and expose the
RTL8211F RGMII clock delay mode in devicetree.
Some MAC drivers, such as Renesas RA RMAC, can provide part of
the RGMII delay themselves. Boards then need a way to avoid
enabling the same delay in the PHY.
Keep the fallback at RX and TX delay enabled, matching the old
driver behavior for existing users.
Signed-off-by: Shan Pen <bricle031@gmail.com>
The LP_UART parameter configuration enabled the bus clock and
selected the source clock without asserting the reset register
in between. After a soft reset the LP_UART hardware could keep
stale state from the previous boot, leading to garbled output
until a power cycle cleared the registers.
Insert the missing lp_uart_ll_reset_register() between the bus
clock enable and the source clock selection.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The driver only enabled the LCD core clock, so operation relied
on the LCD bus clock being left enabled by ROM or the
bootloader. If the bus clock is gated by a later peripheral
teardown the LCD registers become inaccessible.
Enable the LCD bus clock and assert the reset register before
initializing the HAL.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
clock_control_on() only enables the bus clock and asserts the
reset. The matching core clock must be enabled separately on
chips with independent reset and clock control, otherwise the
register writes that configure the sampling clock can stall
the bus.
Add an explicit i2s_ll_enable_core_clock() call right after
clock_control_on().
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The DMA path enabled the SARADC bus clock directly with
adc_ll_enable_bus_clock() and adc_ll_reset_register(), which
skips the function clock on chips where reset and clock control
are independent and also skips the temperature sensor register
preservation. On ESP32-C3 this left the SAR analog block in a
state where writing the digital controller timer enable bit
stalled the bus and hung the driver on the first DMA read.
Replace the manual sequence with adc_apb_periph_claim() and add
sar_periph_ctrl_adc_reset() at the start of every DMA read.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The driver guarded the manual FSM recovery path with
SOC_I2C_SUPPORT_HW_FSM_RST, which no longer exists. The actual
HAL macro is I2C_LL_SUPPORT_HW_FSM_RST, so the guard always
evaluated false and the hardware FSM reset shortcut was never
taken on chips that support it.
Switch the guard to the new name.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
