Add SPI pin for the nucleo_f401re pinmux.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add a SPI master and slave driver for the L4, F4 and F3 STM32
SoCs families.
Change-Id: I1faf5c97f992c91eba852fd126e7d3b83158993d
Origin: Original
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Tested-by: Lee Jones <lee.jones@linaro.org>
As not all drivers support interrupts we don't have a means to know if
we can allow UART_INTERRUPT_DRIVEN to be enabled and thus various
Kconfig options that select UART_INTERRUPT_DRIVEN. Some drivers have a
interrupts, however not all do. So introduce a Kconfig option to let us
know what the driver actually supports.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In added mode flash operation are performed in timeslice
(in radio idle time).
Kconfig for mode enabling CONFIG_SOC_FLASH_NRF5_RADIO_SYNC.
Erase and write API implementations were rewritten and preserved against
concurrent execution.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add configuration, documentation, pinmux, fixup and dts support for
STM32F103x8 based Minimum System Development board.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
as config SPI_CS_GPIO was selecting GPIO instead it
should just depend on it. This patch is a fix for
ZEP-2071 jira.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
patch enables qmsi serial driver to pick baudrate and name
from device tree instead of Kconfig for UART0 and UART1
instance
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
The esp-idf package contains on the BSP a definition of the BIT macro
unconditionally #defined when rom/uart.h is #included. When Zephyr's
uart.h (which pulls in include/misc/util.h) that conditionally
This generates a compile warning on the re-definiton of BIT by the
esp-idf package.
Thus include uart.h after esp-idf's rom/uart.h to have BIT not
re-defined thanks to Zephyr's conditional definition.
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
This is a minimal driver enabling console output during the port
bringup. While the driver works, only one of the three UART devices
are supported, and there isn't any way to change any parameters or
use interrupts. This will most likely be superceded by a proper
driver after the port has matured.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Update driver to use DTS-generated #defines for port names,
and not obsolete Kconfig variables.
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
L4 write access requires 64 bits alignment
while L4 read access does not require any alignment.
To support specific check according to read/write,erase
a parameter is added to stm32_valid_range.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
L4 have 64 bits write access.
The cast to 64 bits data address in write_dword
requires 3 right shifts on i (byte index) else the
data taken are wrong for i different from 0
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
We always have UART_IRQ_FLAGS set to 0, so just call IRQ_CONNECT with a
0 argument for the flags, and remove the UART_IRQ_FLAGS. This is
towards support for using the driver on the TI CC2650. (we add a
comment about that as well).
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit fixes the compilation error that occurs if both UART
ports on the FE310 SoC are enabled. The error occurs due to the
missing function definition of uart_fe310_irq_cfg_func_1 .
Signed-off-by: Jens Peter Schroer <jens@manetos.com>
Refactor internals of IPM driver removing bitfields and byte access of
32 bit registers.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The current method of accessing 32-bit data and control registers does
not work for all quark architectures. Sometimes writing to those
registers byte-by-byte results in last byte occupying whole 32 bit
register.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I43a9d278c3f2c936a714263626722f630367b663
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Following migration of stm32f1xx series clock control driver to
STM32Cube LL API, cleanup stm32 code base in order to take into
account that this is the only clock driver available for stm32
family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following introduction of stm32cube LL based clock control driver,
remove references to former native driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before introduction of LL based clock control for stm32f1xx series,
prepare gpio driver to provide useful definition for new API
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Align stm32f1xx series clock driver to other parts of stm32 family.
Driver support both Connectivity and Density lines of stm32f1 series,
that are based on different Reset and Clock Control architectures.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The Nucleo STM32F413 board is missing the default pinmux for PWM2 on
PA0, as stated in the doc. The same pinmux is also done for other
similar Nucleo board. So add it!
Change-Id: I2086c0a4ce65d68455a0978570f118e965f4c6ca
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Atmel SAM3X series has been recently converted to use ASF
and should now use common SAM family drivers. The atmel_sam3
serial driver will be removed in the future.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Fix nRF RTC timer from returning more than actual cycles
in _timer_cycle_get_32, under race condition when ISR
announces to kernel.
Jira: ZEP-2229
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Instead of NULL terminated buffer arrays, let's add a parameter for each
that tells the number of spi_buf in it.
It adds a little bit more complexity in driver's side (spi_context.h)
but not on user side (bufer one has to take care of providing the NULL
pointer at the end of the array, now he requires to give the count).
This will saves a significant amount of bytes in more complex setup than
the current dumb spi driver sample.
Fix and Use size_t everywhere (spi_context.h was using u32_t).
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The code was so far requesting 5 ms refresh timer, however with a
default TICKS_PER_SECOND=100 this was always rounded up to 10 ms,
causing some flickering. The closest TICKS_PER_SECOND that will give
flicker-less display but also give optimal ms-to-ticks calculations is
250, so change the timer to match that. After this change any code
using the display is recommended to set 250 as ticks per second.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
