Use auto-generated device tree macros in LSM6DSL driver to avoid
usage of dts.fixup code for it.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Added UART4 alternate pin function for L4 µC for PC10 and PC11.
Corrected naming of previously defined UART4 TX and RX defines.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Moved UART interrupt dependencies from concrete driver to
the modem receiver as it uses UART interrupt functions within.
This allows developing other UART interrupt based modems without
the need to depend on the aforementioned features explicitly.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.
As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
Add a Peripheral Clock Controller (PCC) driver. This gates and ungates
clocks to various peripherals on the SoC.
Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:
- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral
The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.
Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
Some extensions to the multi-level interrupt controller are required
to support SoCs with more than four level 2 interrupt "aggregators".
Extend existing support to allow at most 8 level 2 or level 3
aggregators. Use Kconfig macro templates to cut down on boilerplate.
Try to clarify some aspects of the Kconfig help while we're at it, and
change the type of options which count things or are table offsets
from "hex" to "int", so that the generated .config is easier to read.
Finally, make some improvements to gen_isr_tables.py while we are
here. In particular, move some assignments around to cut down on
duplicated work, don't check for symbols we know must exist, and
improve the debug logging output's readability.
Signed-off-by: Marti Bolivar <marti@foundries.io>
It's not an error if a driver does not implement callback related
function. Let's return -ENOTSUP relevantly.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It needs to verify if the callback was not already installed, and if so:
if is was in controller's list.
It should return an error in case the node is not found though it was
requested to be removed.
If already inserted, it will be silently removed but added again, to
avoid circular list as stated in the bug.
Fixes#11394
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Complete code factorization in stm32 exti drivers.
Add return value in case line is not implemented.
Except returned error code, refactor has been done iso-feature
compared to previous code. Hence error is reported only when
support was not available on previous series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use Kconfig named choice for TRIGGER_MODE in order to easy
up the trigger mode selection in default configurations
for boards using this sensor driver.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The PLLR parameter in LL_RCC_PLLI2S_ConfigDomain_I2S() API should
be selected among the following list of (already shifted) values:
* @arg @ref LL_RCC_PLLI2SR_DIV_2
* @arg @ref LL_RCC_PLLI2SR_DIV_3
* @arg @ref LL_RCC_PLLI2SR_DIV_4
* @arg @ref LL_RCC_PLLI2SR_DIV_5
* @arg @ref LL_RCC_PLLI2SR_DIV_6
* @arg @ref LL_RCC_PLLI2SR_DIV_7
This commit fixes PR #12609.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
We now generate CS GPIO defines from the DTS that we can utilize. We
needed to slightly update the #defines in the driver from:
DT_MICROCHIP_ENC28J60_0_CS_GPIOS_{PIN,CONTROLLER} to
DT_MICROCHIP_ENC28J60_0_CS_GPIO_{PIN,CONTROLLER}
Fixes#12640
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Share lis2dh driver among few accelerometer sensors that has
same register interface: LIS2DH, LIS3DH, LSM303DLHC, LIS2DH12,
LSM303AGR.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Use auto-generated device tree macros in LIS2DH driver to avoid
usage of dts.fixup files. The triggered interrupt part has been
slightly hacked to automatically understand whether only int1 is
configured or both int1 and int2.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Move to using the generated DT_INVENTEK_ESWIFI_ESWIFI0_CS_GPIO_pin and
DT_INVENTEK_ESWIFI_ESWIFI0_CS_GPIO_CONTROLLER defines and drop the
DT_ESWIFI0_CS_GPIOS_PIN & DT_INVENTEK_ESWIFI_ESWIFI0_CS_GPIO_PIN from
dts_fixup.hl
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Not necessary with gcc, and Zephyr is inconsistent about using the
qualifier, but making the intent explicit is a good thing.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The existing implementation of z_clock_set_timeout() calculates the
compare value based on a complex series of operations including an
unconditional integer division and multiplication intended to ensure the
compare value is aligned to a tick boundary. On the nRF51 this division
requires a call to an outline function with a data-dependent execution
time.
In the common case where the timeout is set less than one tick past the
last observed tick the devision can be elided, as can several extra
operations intended to deal with fractional ticks.
The code also failed to account for a ticks-per-cycle that violated the
minimum delay required to guarantee a compare value would result in a
match without wrapping. The minimum delay was also unreasonably long
(about 1 ms). Reduce it to a more reasonable value to allow for a
higher ticks-per-second, and diagnose attempts to set the tick frequency
above the supported maximum (8192 Hz).
Finally, move the parts of the compare calculation that are not
dependent on the live counter value out of the locked region.
Prior to this change the observed time between the irq_lock() and
irq_unlock() in z_clock_set_timeout() on the nRF51 ranged between 5 us
and 8 us.
With the revised algorithm the observed lock duration is between 2.16 us
(1024 Hz) and 2.88 us (100 Hz) in the common case that the compare is
set within the current tick. If the compare is set late the duration
will be higher, but no greater than the previous implementation.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The RTC COUNTER register doesn't care that it receives a value larger
than it can hold; it'll discard the bits internally. No need to spend
cycles doing it manually.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
spinlock gains us nothing on an architecture that doesn't support SMP.
Use the standard irq_lock() API so when we search for conditions that
may decrease ISR responsiveness we can find them.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Some of the events from USBD peripheral (i.e. cable disconnect)
were handled in IRQ context and some of them (i.e. ep r/w events) in
system workqueue (inherited from initial driver implementation).
This may lead to race condition in some specific situations.
Currently, all of the events are enqueued in ISR and processed in
workqueue. Driver is reinitialized on queue overflow and queue size
is configurable in KConfig.
Fixes#12016
Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
Supported PWM at pins A0, D3, D5 and D6 which are also Arduino
compatible. Also the onboard red LED can be used with PWM.
The basic/{fade_led, blink_led} samples to apply to this board
seemlessly and operate on the onboard red LED.
Also supported RTC.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
In case of TX IRQ pending,
uart_stm32_irq_is_pending() function always return 0,
because "is TXE enabled ?" is checked instead of "is TC enabled ?".
Signed-off-by: Benoit Leforestier <benoit.leforestier@gmail.com>
Behavior of function gpio_stm32_configure has been modified
during driver factorization. Various gpio settings (speed, mode, ..)
are applied conditionally while they used to be applied in sequence,
unconditionally before this change. As a consequence some
combinations of configurations are no more applied (like speed for
alternate mode). This of course has impact in some use cases.
Rework functions in order to apply settings unconditionally. Take
advantage of the change to reduce code size.
This change impacts all SoCs except F1 series.
Fixes#12544
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added new UART API, that allows for longer transmissions, leaves
IRQ handling on driver side and allows for DMA usage.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Number of USB endpoints is set via DTS, nevertheless USB driver
tries to enable all endpoints as it uses number of endpoints from
nRFx.
This commit makes driver enable only these endpoints that were
enabled in DTS.
Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
Add support to STM LIS2DS12 3-axis accelerometer driver.
The driver support I2C and SPI bus communication and both
polling and drdy trigger mode.
Currently it uses high resolution only as power mode.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The SAM E70 Ethernet driver uses scatter gather DMA to transmit data.
Each fragment of a network packet is mapped from a set of descriptors
that is used by the controller to do the DMA transfer. Each descriptor
contain an address and a length/status. The important status bits are
GMAC_TXW1_LASTBUFFER to indicate the last fragment of a packet and
GMAC_TXW1_USED to indicate that a descriptor has been processed by the
controller.
When starting a transmission, the controller start at the descriptor
after the last one that has been processed. If the descriptor is NOT
flagged by GMAC_TXW1_USED, it sends a first packet by sending all the
fragments up to a descriptor flagged with GMAC_TXW1_LASTBUFFER. The
first descriptor of a packet *and only the first descriptor of a packet*
is then modified to flag it with GMAC_TXW1_USED and to provide a status
(mostly related to errors and checksum offloading). It then continues
with the next packet and so on and only stops if the next descriptor
after GMAC_TXW1_LASTBUFFER is flagged with GMAC_TXW1_USED.
Therefore in order for the controller to stop processing descriptors,
the strategy is to flag the next descriptor after the last fragment to
be sent with GMAC_TXW1_USED. When the next packet has to be queued, the
flag can be removed before starting a transmission.
This is what is currently done in the current driver. However there is a
small race condition in the implementation: if packets are queued fast
enough, the controller is still sending the fragment of the previous
packet when the descriptor are written. When writing the first
descriptor, the GMAC_TXW1_USED flag is removed. This is done after
writing the address (with a memory barrier) so that looks safe. However
given that the GMAC_TXW1_USED flag is only added by the controller to
the first descriptor of a packet it means the next descriptor might
have it cleared. In that case the descriptor is processed, and a junk
packet is sent. That also desynchronize eth_tx and tx_complete as one
or more packets than expected are transmitted.
In order to fix that the strategy is slightly changed to initially write
the first descriptor with the GMAC_TXW1_USED flag set. Once all the
descriptors from the packet are written the bit is cleared (after a
memory barrier). Then the transmission can be started safely.
The patch also does a small optimization writing the next descriptor
with only the GMAC_TXW1_USED bit set instead of setting this bit. As
this will be a non-cached area, it's better avoiding a read followed
by a write if not necessary.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
If a pkt has more frags than the number of TX descriptors, we end up in
a deadlock situation, as the whole packet and thus all the frags have to
be mapped in the descriptors at once. That is why the number of
descriptors is defined as CONFIG_NET_BUF_TX_COUNT + 1.
This wrongly assumes that only TX buffers can be used to send data,
however the packets might also come from the RX buffers, like for
example with ICMPv4.
Therefore define the number of descriptors as the maximum of
CONFIG_NET_BUF_RX_COUNT + 1 and CONFIG_NET_BUF_TX_COUNT + 1. This fixes
a deadlock when CONFIG_NET_BUF_TX_COUNT is much smaller than
CONFIG_NET_BUF_RX_COUNT.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The current SAM E70 Ethernet driver sometimes get stuck if the stack
has to send 2 packets in a row, for example an ack for the just received
data + answer data.
The problem is the following one:
1) The first packet goes through eth_tx, one tx_desc_sem semaphore is
taken, and the tx_timeout_work delayed work is submitted.
2) The second packet also goes through eth_tx, another tx_desc_sem
semaphore is taken, and the tx_timeout_work delayed work is not
started because there is already one already submitted.
3) The first packet has been sent, one tx_desc_sem semaphore is given
and the tx_timeout_work delayed work is cancelled.
4) The second packet has been sent but given the delayed work has
already been cancelled, tx_completed is not called: the tx_desc_sem
semaphore is not given back and the network packet is not
unreferenced.
The whole timeout concept probably has to be reworked. In the meantime
it is probably better to just drop the timeout code instead of keeping
the driver broken. We can only get stuck on the TX path if there is a
bug in the driver or a hardware malfunction. It might happen, but with
the less probability then the current hangs. In addition it just hides
the real issues and prevent them to be fixed.
This commit therefore just remove the timeout code in the TX path.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Cleanup dependencies in Kconfig and convert some top-level options to
menuconfig. guard all dependent options with if instead of using
'depends on' for readibility.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup dependencies in Kconfig and convert some top-level options to
menuconfig. guard all dependent options with if instead of using
'depends on' for readibility.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
