interrupt_controller: gic: Add support for the GIC400
The GIC400 is a common interrupt controller that can be used with the Cortex A and R series processors. This patch adds basic interrupt handling for the GIC, but does not handle multiple routing or priorities. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen
Ioannis Glaropoulos
parent
b34b00d6ec
commit
571d3b54db
5 changed files with 306 additions and 0 deletions
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_ARCV2_INTERRUPT_UNIT arcv2_irq_unit.c)
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zephyr_sources_ifdef(CONFIG_GIC gic-400.c)
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zephyr_sources_ifdef(CONFIG_IOAPIC ioapic_intr.c)
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zephyr_sources_ifdef(CONFIG_LOAPIC loapic_intr.c system_apic.c)
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zephyr_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR loapic_spurious.S)
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@ -147,6 +147,13 @@ config DW_ICTL_INIT_PRIORITY
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help
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DesignWare Interrupt Controller initialization priority.
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config GIC
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bool "ARM Generic Interrupt Controller (GIC)"
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depends on CPU_CORTEX_R
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help
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The ARM Generic Interrupt Controller works with Cortex-A and
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Cortex-R processors.
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source "drivers/interrupt_controller/Kconfig.stm32"
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source "drivers/interrupt_controller/Kconfig.multilevel"
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246
drivers/interrupt_controller/gic-400.c
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246
drivers/interrupt_controller/gic-400.c
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@ -0,0 +1,246 @@
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/*
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* Copyright (c) 2018 Marvell
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* Copyright (c) 2018 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <sw_isr_table.h>
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#include <irq_nextlevel.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define DT_GIC_DIST_BASE DT_INST_0_ARM_GIC_BASE_ADDRESS_0
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#define DT_GIC_CPU_BASE DT_INST_0_ARM_GIC_BASE_ADDRESS_1
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#define GICD_CTRL (DT_GIC_DIST_BASE + 0)
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#define GICD_TYPER (DT_GIC_DIST_BASE + 0x4)
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#define GICD_IIDR (DT_GIC_DIST_BASE + 0x8)
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#define GICD_IGROUPRn (DT_GIC_DIST_BASE + 0x80)
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#define GICD_ISENABLERn (DT_GIC_DIST_BASE + 0x100)
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#define GICD_ICENABLERn (DT_GIC_DIST_BASE + 0x180)
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#define GICD_ISPENDRn (DT_GIC_DIST_BASE + 0x200)
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#define GICD_ICPENDRn (DT_GIC_DIST_BASE + 0x280)
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#define GICD_ISACTIVERn (DT_GIC_DIST_BASE + 0x300)
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#define GICD_ICACTIVERn (DT_GIC_DIST_BASE + 0x380)
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#define GICD_IPRIORITYRn (DT_GIC_DIST_BASE + 0x400)
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#define GICD_ITARGETSRn (DT_GIC_DIST_BASE + 0x800)
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#define GICD_ICFGRn (DT_GIC_DIST_BASE + 0xc00)
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#define GICD_SGIR (DT_GIC_DIST_BASE + 0xf00)
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#define GICC_CTRL (DT_GIC_CPU_BASE + 0x00)
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#define GICC_PMR (DT_GIC_CPU_BASE + 0x04)
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#define GICC_BPR (DT_GIC_CPU_BASE + 0x08)
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#define GICC_IAR (DT_GIC_CPU_BASE + 0x0c)
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#define GICC_EOIR (DT_GIC_CPU_BASE + 0x10)
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#define GICC_ENABLE 3
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#define GICC_DIS_BYPASS_MASK 0x1e0
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#define NO_GIC_INT_PENDING 1023
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#define GIC_SPI_INT_BASE 32
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#define GIC_INT_TYPE_MASK 0x3
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#define GIC_INT_TYPE_EDGE (1 << 1)
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struct gic_ictl_config {
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u32_t isr_table_offset;
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};
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static void gic_dist_init(void)
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{
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unsigned int gic_irqs, i;
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gic_irqs = sys_read32(GICD_TYPER) & 0x1f;
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gic_irqs = (gic_irqs + 1) * 32;
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if (gic_irqs > 1020)
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gic_irqs = 1020;
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/*
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* Disable the forwarding of pending interrupts
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* from the Distributor to the CPU interfaces
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*/
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sys_write32(0, GICD_CTRL);
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/*
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* Set all global interrupts to this CPU only.
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*/
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 4)
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sys_write32(0x01010101, GICD_ITARGETSRn + i);
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 16)
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sys_write32(0, GICD_ICFGRn + i / 4);
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/* Set priority on all global interrupts. */
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 4)
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sys_write32(0, GICD_IPRIORITYRn + i);
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/* Set all interrupts to group 0 */
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 32)
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sys_write32(0, GICD_IGROUPRn + i / 8);
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as these enables are banked registers.
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*/
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for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 32) {
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sys_write32(0xffffffff, GICD_ICACTIVERn + i / 8);
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sys_write32(0xffffffff, GICD_ICENABLERn + i / 8);
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}
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/*
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* Enable the forwarding of pending interrupts
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* from the Distributor to the CPU interfaces
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*/
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sys_write32(1, GICD_CTRL);
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}
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static void gic_cpu_init(void)
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{
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int i;
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u32_t val;
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/*
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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sys_write32(0xffffffff, GICD_ICACTIVERn);
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sys_write32(0xffff0000, GICD_ICENABLERn);
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sys_write32(0x0000ffff, GICD_ISENABLERn);
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4)
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sys_write32(0xa0a0a0a0, GICD_IPRIORITYRn + i);
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sys_write32(0xf0, GICC_PMR);
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/*
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* Enable interrupts and signal them using the IRQ signal.
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*/
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val = sys_read32(GICC_CTRL);
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val &= GICC_DIS_BYPASS_MASK;
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val |= GICC_ENABLE;
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sys_write32(val, GICC_CTRL);
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}
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static void gic_irq_enable(struct device *dev, unsigned int irq)
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{
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int int_grp, int_off;
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irq += GIC_SPI_INT_BASE;
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int_grp = irq / 32;
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int_off = irq % 32;
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sys_write32((1 << int_off), (GICD_ISENABLERn + int_grp * 4));
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}
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static void gic_irq_disable(struct device *dev, unsigned int irq)
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{
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int int_grp, int_off;
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irq += GIC_SPI_INT_BASE;
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int_grp = irq / 32;
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int_off = irq % 32;
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sys_write32((1 << int_off), (GICD_ICENABLERn + int_grp * 4));
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}
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static unsigned int gic_irq_get_state(struct device *dev)
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{
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return 1;
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}
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static void gic_irq_set_priority(struct device *dev,
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unsigned int irq, unsigned int prio, u32_t flags)
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{
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int int_grp, int_off;
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u8_t val;
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irq += GIC_SPI_INT_BASE;
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/* Set priority */
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sys_write8(prio & 0xff, GICD_IPRIORITYRn + irq);
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/* Set interrupt type */
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int_grp = irq / 4;
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int_off = (irq % 4) * 2;
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val = sys_read8(GICD_ICFGRn + int_grp);
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val &= ~(GIC_INT_TYPE_MASK << int_off);
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if (flags & IRQ_TYPE_EDGE)
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val |= (GIC_INT_TYPE_EDGE << int_off);
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sys_write8(val, GICD_ICFGRn + int_grp);
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}
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static void gic_isr(void *arg)
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{
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struct device *dev = arg;
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const struct gic_ictl_config *cfg = dev->config->config_info;
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void (*gic_isr_handle)(void *);
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int irq, isr_offset;
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irq = sys_read32(GICC_IAR);
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irq &= 0x3ff;
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if (irq == NO_GIC_INT_PENDING) {
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printk("gic: Invalid interrupt\n");
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return;
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}
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isr_offset = cfg->isr_table_offset + irq - GIC_SPI_INT_BASE;
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gic_isr_handle = _sw_isr_table[isr_offset].isr;
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if (gic_isr_handle)
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gic_isr_handle(_sw_isr_table[isr_offset].arg);
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else
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printk("gic: no handler found for int %d\n", irq);
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/* set to inactive */
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sys_write32(irq, GICC_EOIR);
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}
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static int gic_init(struct device *unused);
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static const struct irq_next_level_api gic_apis = {
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.intr_enable = gic_irq_enable,
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.intr_disable = gic_irq_disable,
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.intr_get_state = gic_irq_get_state,
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.intr_set_priority = gic_irq_set_priority,
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};
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static const struct gic_ictl_config gic_config = {
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.isr_table_offset = CONFIG_2ND_LVL_ISR_TBL_OFFSET,
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};
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DEVICE_AND_API_INIT(arm_gic, DT_INST_0_ARM_GIC_LABEL,
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gic_init, NULL, &gic_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &gic_apis);
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/**
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*
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* @brief Initialize the GIC device driver
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*
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*
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* @return N/A
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*/
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#define GIC_PARENT_IRQ 0
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#define GIC_PARENT_IRQ_PRI 0
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#define GIC_PARENT_IRQ_FLAGS 0
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static int gic_init(struct device *unused)
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{
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IRQ_CONNECT(GIC_PARENT_IRQ, GIC_PARENT_IRQ_PRI, gic_isr,
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DEVICE_GET(arm_gic), GIC_PARENT_IRQ_FLAGS);
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/* Init of Distributor interface registers */
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gic_dist_init();
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/* Init CPU interface registers */
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gic_cpu_init();
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return 0;
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}
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29
dts/bindings/interrupt-controller/arm,gic.yaml
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29
dts/bindings/interrupt-controller/arm,gic.yaml
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@ -0,0 +1,29 @@
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#
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# Copyright (c) 2018 Marvell
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: ARMv7-R Generic Interrupt Controller
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description: >
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This binding describes the ARM Generic Interrupt Controller.
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inherits:
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!include base.yaml
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properties:
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compatible:
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constraint: "arm,gic"
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reg:
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category: required
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label:
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category: required
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"#cells":
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- irq
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- priority
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- flags
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...
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23
include/dt-bindings/interrupt-controller/arm-gic.h
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23
include/dt-bindings/interrupt-controller/arm-gic.h
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2018 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __DT_BINDING_ARM_GIC_H
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#define __DT_BINDING_ARM_GIC_H
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/* CPU Interrupt numbers */
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#define GIC_INT_VIRT_MAINT 25
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#define GIC_INT_HYP_TIMER 26
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#define GIC_INT_VIRT_TIMER 27
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#define GIC_INT_LEGACY_FIQ 28
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#define GIC_INT_PHYS_TIMER 29
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#define GIC_INT_NS_PHYS_TIMER 30
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#define GIC_INT_LEGACY_IRQ 31
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#define IRQ_TYPE_LEVEL 0x0
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#define IRQ_TYPE_EDGE 0x1
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#define IRQ_DEFAULT_PRIORITY 0xa
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#endif
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