Functions related to string manipulation that were defined in
`common/log.h` has been moved to the `common/bt_str.h` file and their
implementation in `common/bt_str.c`.
Files that were using those functions has been updated consequently.
Signed-off-by: Théo Battrel <theo.battrel@nordicsemi.no>
Zephyr implementation is limited to 4 IRQ per GPIO bank when up to 8 is
theoritically possible.
It is now possible to use until 8 IRQ per GPIO bank. This can be
achieved with minimal effort in a device tree overlay:
&gpio0 {
interrupts = <4 2>,<5 2>,<6 2>,<7 2>,<32 2>,<33 2>;
};
&gpio1 {
interrupts = <34 2>,<35 2>;
};
Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
The PWM definitions for Atmel SAM SoCs can differ slightly.
This commit adds support for the PWM defines used by SAM4S.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Cache written data to avoid rewriting same flash page multiple times
when writing subsequent flash pages. The cache is used for reads to
account for reading not yet committed (i.e. dirty) page data. Speeding
up reads is not intention of this patch and therefore the read path
does not modify cache state.
Fixes: #30212
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Rename the CAN loopback driver receive function to make the code easier to
understand. Add proper check against NULL for RX callback function
pointers.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Set default of DISK_DRIVER_SDMMC Kconfig based on the devicetree.
This should avoid having to set the kconfig at the board level
in order to use sdmmc.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Update power_domain drivers to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove one reference in prj.conf that is no longer needed.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Brackets were originally used in the sensor info shell command output to
make it obvious when a field is a null string, however they incorrectly
suggest that a field is an array. Remove the brackets and conditionally
print "(null)" instead.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Add support for configuring CAN emulation support in QEMU. For now, the
only supported CAN controller is the single-channel Kvaser PCIcan PCI card.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This seems to have caused CI failures and its unclear why just yet
so revert instead.
This reverts commit cbee9e9fdd8060d0ca4e91037b3f99f631e4b1a5.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Fix the enabling of the independant IO supply.
Function LL_PWR_EnableVddIO2 is called LL_PWR_EnableVDDIO2 on U5.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Update Intel ADSP timer driver to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove setting 'default y' for the timer driver in
Kconfig.defconfig.series as that is now handled in the driver Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Mark the timer as having a lock free read of the cycle count
so that spin lock debugging can include lock time asserts.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Update IPM drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Support multiple DTS instances in the C code, also
just initialize devices that are not disabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Expanded the enc28j60 driver to update its carrier status
whenever the Ethernet cable is plugged in or out. I used the
enc424j600 driver as reference, as this driver already
included this functionality. The driver will now take
the interface offline whenever the cable is not plugged in
and stop sending packets. The respective events are also
generated for use in the application. I tested it locally
on my nRF52840 based gateway board using the enc28j60 network
chip. Everything worked as expected.
Signed-off-by: Paul Jans <paul.jans.1999@hotmail.com>
Fixes#51214
Adds a new conditional shell command to the sensor shell to get data
from the sensor info iterable section, such as vendor and model name,
for all sensors.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Adds an iterable section in ROM to hold constant information, such as
vendor and model name, for all enabled sensor driver instances. This
will be used by the future sensor subsystem to enumerate all available
sensors in the system.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
The ESP32 series MCUs allow to set a timeout which triggers an error
if the SCL line is unchanged for the specified amount of time.
By default, the ESP-IDF HAL sets the timeout to an arbitrary value of
10 times the bus cycle.
This is not sufficient for chips like the TI bq76952, which pulls the
SCL line low (clock stretching) for several 100 µs.
The timeout should also not be dependent on the chosen bitrate, as it
is defined by the time a chip needs for internal calculation before it
can provide requested data or continue communication.
This commit adds a property to devicetree to allow configuration of
the scl timeout. This value is set via direct register access, as the
ESP-IDF HAL does not provide access to the enable bit and does not
give any information about the maximum size of the timeout (defined
in I2C clock cycles in the register).
Fixes#51351
Signed-off-by: Martin Jäger <martin@libre.solar>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x CPU and fast peripheral (QMSPI and PK) are
clock source is based upon an OTP setting. Add logic to adjust
clock source based on OTP value. If the OTP value is ever changed
this fix will allow calcluation of correct clock rate.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove all obsolete DISK_FLASH* Kconfig options.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Use devicetree to obtain information for all zephyr flash disks.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
In order to avoid using multiple sources of truth for the platfom's
endianness, convert the in-tree code to use the (BIG|LITTLE)_ENDIAN
Kconfig variables exclusively, instead of the compiler's
__BYTE_ORDER__.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
GICR_TYPER is a 64 bit register. On AArch32 when one uses sys_read64(),
this results in ldrd instruction. When Zephyr runs as a VM, 'LDRD'
instruction on an emulated MMIO region gets trapped to the hypervisor as
data abort.
Refer the following paragraph from ARM DDI 0487G.b ID072021 :-
Section - "ISS encoding for an exception from a Data Abort",
"For other faults reported in ESR_EL2, ISV is 0 except for the following
stage 2 aborts:
AArch32 instructions where the instruction:
— Is an LDR, LDA, LDRT, LDRSH, LDRSHT, LDRH, LDAH, LDRHT, LDRSB, LDRSBT,
LDRB, LDAB, LDRBT, STR, STL, STRT, STRH, STLH, STRHT, STRB, STLB, or STRBT
instruction."
As 'LDRD' is not in the list, so ISV==0. This implies that Arm could not
decode the instruction for the hypervisor (in EL2) to execute it.
Thus, we have abstracted this read into arm_gic_get_typer().
For AArch64, we use sys_read64() as before.
For AArch32, we use sys_read32() twice to read the lower and upper 32 bits
of GICR_TYPER.
Thus, we ensure that when the access is trapped for AArch32, Arm generates
a valid ISS so that hypervisor can execute it.
Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
To avoid legacy extended adv repots blocking important
events or work, mark them as discaradble.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
Print the error messages about the state of the host register
when the I2C transfers fail. This is useful for debugging.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
DMIC does not need to use SOFT_RESET bit to start collecting data if
periodic_start bit is enabled.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
