Add the flash channel support by implementing the controller attached
flash sharing APIs, including flash_read, flash_write, and flash_erase.
For flash_read, the max data payload the module can support is 64 bytes
in one transaction.
For flash_write, the max data payload the module can support is 16
bytes in one transaction.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
DT node "st,stm32f105-pll2-clock" already exists but was not actually used
and PLL2 was not being configured.
PLL2 is available on STM32F105/F107 and should be turned off after turning
off PLL and turned on before turning on PLL again since PLL2 can be
used as a source for PLL. Source for PLL2 is always HSE.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
Fixes an issue with outgoing mcumgr frames that are larger than the
transport MTU size whereby they would wrongly be split up into multiple
frames with multiple start frame headers, which affected SMP over
console transports.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add support to at86rf212[b] sub-giga devices. This work enables use of
pages 0, 2 and 5 in accordance with IEEE-802.15.4/2003/2006/2011. The
proprietary speeds can be object of future work.
Note: It is recommended that user define a power table for better
performance, low emissions and to save power. A reference power table
can be found in the datasheet and should be used for tests only and
not on a final product.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current version of power table is hardcoded in the driver which is a
problem when use devices in production. This change remove all hardcode
from driver and reimplement the feature to allow people create a table
which is defined in devicetree. The big advantage is that each board can
define their own table based on lab tests and allows use of FEM devices
inclusive.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
In old way, gic_rdists[cpu] is calculated via MPIDR_TO_CORE(), but in
real hardware, MPIDR_TO_CORE() isn't a value increment from 0 one by
one, and that will lead gic_rdists[cpu] to point to a wrong address.
GICv3 provides the register GICR_TYPER[1] and it has a field named
Affinity_Value. This field can help to determine where gic_rdists[cpu]
should point.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
1. Move the defines from usb_dc_mcux.h to usb_device_config.h
and fsl_os_abstraction.h. These headers are used by
the SDK USB driver. usb_dc_mcux.h header file is not longer
needed and hence deleted.
2. Delete the Zephyr implementation of the usb_device_struct
driver and use the one implemented inside the SDK USB
driver. This requires updating the references to
usb_device_struct inside the USB driver
3. Move defines and structures used by the driver
out of the header file that is included by the SDK and
into the MCUX USB driver.
4. Use end point defines provided by Zephyr instead of adding
them locally.
5. Add a Kconfig to set the thread stack size
6. Move code to enable interrupts back to usb_attach function.
Interrupts should be enabled after the init is successful,
else we see errors of the ISR getting called before the
init is complete causing Faults
6. Update west.yml to update the NXP HAL to get the updated
SDK USB driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit introduces the 1-wire master driver for maxim ds2485.
The ds2485 master has nearly the same (1-wire) feature set and
i2c-interface as the ds2477.
Therefore the common parts are extracted, but to avoid
any nda troubles only the ds2485 specific part is included.
Compared to older 1-wire masters, the ds2485 supports higher level
commands, supporting multi byte operations, search next, automatic crc
calculation.
In this driver only basic read and write operations are supported,
further hardware features are not yet utilized by the driver.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
In some configurations, a udf instruction may be generated
when compiling code where static global variable lptim_clock_freq is
used as a divisor.
To avoid this, initialize variable on declaration so that compiler
could see that it can't be used uninitialized in this division.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
* Enable hardware flow control on Kconfig
* Enable HSI48 clock on sdmmc_stm32 driver
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
On some stm32 mcus, the LSE is enabled as system clock (LSESYS)
only when the LSEON and LSERDY are both set.
The bit LSESYSEN is set in the RCC BDCR register
and the driver is waiting for the LSESYSRDY to be set.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The baudrate register (BRR) of a stm32 USART cannot be lower than 16.
The baudrate register (BRR) of a stm32 LPUART cannot be lower than 0x300
and greater than 0xFFFFF.
Add assertion to check the range.
This could be the case when configuring a baudrate of 9600 on usart
clocked by LSE (32768Hz).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
USBC port (Port 0/1/2/3) OCP (Over Current Protection) status
should be sent to PCH over eSPI VW index 0x50h. But there is
no dedicated VW register mapped to VW index 0x50h.
In this patch, configuring spare VW register SMVW06 to OCP VW
index 50h.
Signed-off-by: Diwakar C <diwakar.c@intel.com>
This driver provides an interface to SocketCAN interfaces of the Linux
system running a Zephyr application with the native_posix board. These
interfaces may be virtual or actual CAN buses.
Signed-off-by: Martin Jäger <martin@libre.solar>
An `ifdef CONFIG_SOC_SERIES_INTEL_ACE1X` currently always evaluates to
true, as `drivers/mm/mm_drv_intel_adsp_mtl_tlb.c` is only built when
`CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y`, which depends on
`CONFIG_SOC_SERIES_INTEL_ACE1X`. So remove the ifdef.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Instead of using SoC versions, define the information about base and
extended ports on Kconfig, and use this information from there.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Instead of using version of the SoC, declare on Kconfig the need for it,
and use this information to decide upon enabling the code or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Update the GPIO-controlled CAN transceiver driver to use the
DT_HAS_CAN_TRANSCEIVER_GPIO_ENABLED Kconfig symbol to expose the driver and
enable it by default based on devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add emulator functionality to the serial_test driver, so that it can be
used to simulate a device on the other end of the uart.
If you don't set the buffer-size property in the dts node, there should
be effectively no change from the previous behavior.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Introducing the dma transfer (also through dmamux)
to transfer data to/from the NOR octo-flash
With a DMAMUX, the DMA channel is given by the DTS.
Note that STM32U5X does not support DMA here.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This supports three types GD32 FMC flash memory. GD32 FMC v1,
GD32 FMC v2 and GD32 FMC v3.
GD32 FMC v1 for small flash memory, flash size can be up to 512KB.
GD32 FMC v2 for large flash memory, flash size can be up to 3072KB.
GD32 FMC v3 not use page but sector as minimum block, flash size can
be up to 3072KB.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
According to i.MX RT1060 Reference Manual:
While the OR flag is set, no additional data is stored in the data
buffer even if sufficient room exists. To clear OR, write logic 1 to
the OR flag.
Clear OR (Overrun) flag whenever it is set, so that data continues to be
received after potential data overrun.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Add R-Car Gen3 PWM driver.
Clock diviser is automatically adjusted according to requested period
and duty-cycle in order to obtain as much accuracy as possible.
Indeed, in order to improve PWM accurancy, the PWM clock has to fit
the requested period. So use the given period_cycle to define if the
clock as to be adapted. In such case, increase/decrease the clock
diviser to adapt the period_cycle and be sure that it fits into the
10 bits counter of the PWM controller.
Tested on H3ULCB on pwm0 and pwm4.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
For some stm32 devices, the SDMMC clock selection is HSI 48MHz
by default (reset value). It must be enabled before acccessing
the peripheral.
The ErrorCode is reported when Init fails.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is the adaptation of the stm32 SPI driver with DMA
transfer for the stm32u5 soc.
Use the DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
also valid for the stm32U5 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit implements shell support for 1-Wire.
Commands for bus-reset, bit-, byte-, and block- communication,
as well as search and configuration are implemented.
- write_byte, and write_block perform a reset before,
in case the option "-r" is passed.
- using read_io_options() function to parse the reset option,
as this allows to easily add further options in the future.
- configuration type can be specified either as number or as name.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Introducing RaspberryPi Pico ADC driver.
This driver was created with reference to the adc_emul implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
MCO1 is also available on STM32F1 series (on top of STM32F4), allow
selection of MCO1 source with CLOCK_STM32_MCO1_SRC_* Kconfig parameters.
Available MCO1 sources are slightly different between STM32F4
(LSE, HSE, HSI, PLLCLK) and STM32F103 (HSE, HSI, PLLCLK/2, SYSCLK), and
STM32F105/F107 have a few more (EXT_HSE, PLL2CLK, PLLI2SCLK, PLLI2SCLK/2).
MCO1 on STM32F1 does not have a configurable divider (unlike STM32F4),
HAL call only configures source.
STM32F1 do not have MCO2.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
