Rename the local "const struct can_mcan_config *" variables from "cfg" to
"config" to be consistent with Zephyr conventions.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Get rid of the can_mcan_configure_timing() helper function as it provides
no benefit to just having the implementation split in can_mcan_set_timing()
and can_mcan_set_timing_data().
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the driver initialization function to the bottom of the file to be
consistent with Zephyr conventions.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Pass a pointer to the struct device for internal driver functions instead
of passing around a pointer to the register struct.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Reading the temperature calibration data requires disabling the icache
of the stm32h5x mcu.
Else a bus fault error occurs reading Address: 0x8fff8014-0x8fff818
Enable afterwards.
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
When using gpio chip select the clock line seems to get stuck low after
some transactions. When attempting to use other SPI_CSR registers
the peripheral fails to work as expected.
Always using SPI_CSR[0] when using gpio chip selects resolves the issue.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This patch introduces support for NXP S32 CANEXCEL (CANXL) peripheral.
CAN protocol supporting:
- CAN classic
- CAN FD
Remote transmission request is not supported as this feature is not
available on NXP S32 CANXL HAL.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
These variables are now provided by the FindBabbleSim
cmake module, which finds them in the environment or thru
west.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
In some cases, the enable pin may be already enabled by a previous
stage, e.g. bootloader. Therefore, it is not desirable to disable
the pin, as it could cause malfunctioning of the device. Refactor init
procedure so that we pick the right GPIO flags during the first
configuration stage.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some STM32 timers have more than one interrupt available.
When such timer is used it's likely that the first found interrupt
will not be the proper, 'cc' interrupt for input capture.
Existing implementation always connected the first irq, which worked
for timers with single, 'global' interrupt but broke input capture
for advanced timers with more interrupts.
Improve the IRQ connection logic by connecting the 'cc' interrupt
if it exists. Only if not found use the fallback mechanism of taking the
first index
Signed-off-by: Marek Metelski <marek@metelski.dev>
Add another helper function to send VW notification that is
neither a warning or conveys a system state.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Remove all enabling of CONFIG_EMUL_.* in favor of automatically enabling
peripheral emulators based on the compatible string presence in the device
tree and the one true CONFIG_EMUL.
Zephyr has long since moved to a model of enabling drivers based on the
presence of their associated IC's compatible string in the final devicetree
overlay. There is no reason that emulators can't align in just the same
way, and probably ought to to remove superfluous enabling of configs.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
According to the datasheet for Marvell PHY [1], the mode field of the
General Control Register 1 Page 18 occupies bits [2:0]. However, the macro
PHY_MRVL_MODE_CONFIG_MASK specifies the mask as 0x3, which would
correspond only to [1:0]. The code in phy_xlnx_gem_marvell_alaska_cfg()
uses the mask to set the mode field to 0 to set "RGMII (System mode) to
Copper" mode. Unfortunately, different chips have different reset values
(111 or 000) and in first case, the code would set the field to 100,
instead of 000.
Without this change, ethernet on Avnet MicroZed (Marvel Alaska 88E1512 PHY)
does not work.
Signed-off-by: Marek Vedral <vedrama5@fel.cvut.cz>
[1]: https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-ethernet-phys-alaska-88e151x-datasheet.pdf
If the boot loader already switched the system clock to PLL1 we need
to switch back to HSI first and disable PLL1 before we can configure
PLL1. Otherwise the register writes will simply be ignored and we'll
end up with an inconsistent state.
Most of the code has been recycled from `clock_stm32_ll_common.c`.
Signed-off-by: Sascha Silbe <sascha-pgp@se-silbe.de>
Signed-off-by: Sascha Silbe <sascha-pgp@silbe.org>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Code for power level property was accidentally
removed by accident from driver in commit 9921c59f40
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
spi_context_get_next_buf must not divide `len` by `dfs` because, in SPI,
buffer lengths are given in units of data (in this case, 16 bits), not in
bytes.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\cy8cproto_062_4343w board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Added RTC driver that supports Motorola MC146818B
Enabled RTC set/get time and alarm, alarm callback
and update callback.
Counter and RTC uses same hardware in case of
Motorola MC146818, so they can't be used at a time.
Updated stand-alone mc146818 counter dts instances
to support rtc and counter with same compatible
string of "motorola,mc146818" on ia32, atom,
apollo_lake, elhart_lake and raptor_lake platforms.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
By default HSIDIV is set to 0x01, so default frequency is 32 MHz.
This register should be always set based on dts value.
Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
The SAM GMAC driver is not able to use all of the receive buffers
concurrently. Frames larger than (buffer size) * (buffer count - 1) are
silently dropped. Fix it by adding one to MAIN_QUEUE_RX_DESC_COUNT.
Fixes#55701
Signed-off-by: Brandon Del Bel <delbel@umn.edu>
The `config` and `api` members of `struct device` are expected
to be `const`. This also improves reliability, as `config`
and `api` are stored in rom rather than ram, which has the
potential to be corrupted at runtime in the absense of an MMU.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
There are use cases for the pcie_ep driver where we don't
necessarily need the dma functionality. Added ifdef's around
the dma functionality so that it's only available if we
specify the dma engines in the device tree similar to
```
dmas = <&pl330 0>, <&pl330 1>;
dma-names = "txdma", "rxdma";
```
Signed-off-by: Tarun Karuturi <tkaruturi@meta.com>
Signed-off-by: Chris Friedt <cfriedt@meta.com>
This patch adds support for the TI INA3221 current monitor.
This is the datasheet used for reference:
https://www.ti.com/lit/gpn/ina3221
Since this device has three channels, there is a custom attribute to
select which channel is to be used when getting a sample.
Measurements are done on all enabled channels.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Make it possible to use CPOL/CPHA SPI clock modes with the SDHC driver.
Some cards require the clock to switch to low when not active.
Signed-off-by: Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
some floats were getting promoted to doubles or they needed to be
casted as doubles to be used by printf
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Following #56576, the `cs` field in `struct spi_config` is of type
`struct spi_cs_control` instead of a pointer to the same type.
`spi_xec_qmspi_ldma.c:qmspi_xec_init` tries assigning `NULL` to the
`.cs` field through a designated initializer, which causes a compilation
error.
This PR simply removes the `.cs = NULL` line. The designated initializer
will automatically zeroize the underlying GPIO pin info, which should
have the same effect that setting the pointer to NULL did previously.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
Disable the hardware I2C target detection on the IT82xx2 SoC family.
Note: The register setting of I2C target detection is different in
IT81XX2 and IT82XX2 SOC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Simplify the STM32 ADC driver code by using the new ADC resolutions
property in dtsi files.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Remove build asserts in favor of DT enums
- Remove power level property since it is unused by SDK
- Correct voltage ref value in DT to correspond to
chip specific values documented in reference manuals
instead of corresponding to SDK enum names.
- Fix SOC devicetrees affected by these changes.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The MCUX USB device driver currently suffers from
some performance related issues caused by the removal
of the intermediate buffer in commit 4e6f80d37a.
This buffer was essential in the case when some USB
descriptors or data were in a slow access memory,
for example a flash memory accessed over flexspi.
USB DMA as AHB master would try to fetch the data,
but it would be too slow and USB peripheral
could not meet deadlines on the USB bus waiting for it,
and so it would send null packets instead causing errors.
This problem can be fixed by re-introducing an intermediate
buffer in RAM with the data copied from the slow memory by
the core before the USB transfer begins, so that USB DMA
is not responsible for fetching it from flexspi/flash.
Changes to MCUX USB Device Driver:
- Re-add intermediate buffer for USB writes in RAM
- Buffer is not needed for reads, add runtime check
to avoid copy overhead
- Buffer is not needed for platforms with USB RAM,
since the USB RAM itself acts as an intermediate buffer.
Compile with buffer code only when USB RAM is not present on
the platform, to avoid unecessary copy overhead.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This PR will divide the LPTIM clock freq to increase the max timeout.
Only one LPTIM instance is considered for PM timer.
The input freq becomes a fraction of the internal PCLK
source (mainly LSE clock). As the tick per sec does not change,
the minimum lptim counter must always be >0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32U5, when modifying the DIER register of the LPTIM peripheral,
a new write operation to can only be performed when the previous write
operation is completed and before going-on.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
CAVS platforms are not fully integrated with zephyr. Some of the
registers are still programed from SOF side. This feature can be enabled
for those platforms later when integration is fully done.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adding function that is allowing to release ownership of the DMA. When
DSP is no longer using dma instance it ownership can be released.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
