STM32H7X and STM32F4X ETH HAL Drivers now provide a new api.
This commit only adds a new Kconfig option
Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
The transmit mutex is not needed while checking the packet size,
so we acquire the lock after checking the size and
return early if it is too big.
Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
It is possible for nrfx usbd driver to send NRFX_USBBD_EP_ABORTED during
endpoint disable. The event is passed to event handler registered with
nrfx_usbd_init(). The nrfx_usbd_uninit() removes the registered event
handler, replacing it with NULL. If any event is sent after uninit, the
NULL pointer is executed and device crashes.
Do not uninit nrfx usbd driver on detach so it is possible for the
usb_disable() to disable all the endpoints.
Fixes: 460ca86527 ("drivers: usb_dc_nrfx: Always allow endpoint disable")
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Depending on the timing of the edges of the signal to be captured, a timer
overflow interrupt flag may appear in the same ISR as a channel event (1st
or 2nd edge capture complete) flag. Change the timer overflow math to
compensate the timer overflow count based on whether the channel event
happened before or after the overflow flag occured.
For continuous PWM period captures, only the very first edge of the first
period requires an interrupt to be captured. Subsequent "first edges" are
the same edges as the second edge of the previous period. Depending on the
timing of the captured signal, enabling the 1st edge interrupt in this case
can cause the overflow count for subsequent first edges to be captured at
the wrong point in time.
Fixes: #52452
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
AST10x0 series SOCs provide the reset controller through the syscon
hardware block. The current driver supports the reset line assert,
deassert and status for the hardware IPs embedded in the SOC. Each
reset line has an ID that can simply map to a bit in syscon registers
RESET_CTRL0_ASSERT (group 0) or RESET_CTRL1_ASSERT (group 1). Write bits
to RESET_CTRL0_DEASSERT or RESET_CTRL1_DEASSERT will clean the
corresponding bits in RESET_CTRL0_ASSERT or RESET_CTRL1_ASSERT
registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Enable the PSA RNG driver by default. This option
will only be enabled when BUILD_WITH_TFM is enabled
and a device with the required compatible field
(zephyr,psa-crypto-rng) is defined in the device tree.
When a vendor includes such a device and enables the
ENTROPY_GENERATOR subsystem it is fair to assume
that wants to use the PSA Crypto RNG driver.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Add support for regulator mode related APIs to regulator shell, so that
the user can select new operation modes for the regulator and configure
target voltages
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Cleanup regulator shell to use strtol() over atoi(), as strtol features
error detection. Remove device_is_ready() checks, and replace them with
NULL checks as device_get_binding() calls device_is_ready() interally
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The I2C API already provides APIs to read/modify registers, so there is
no need to provide custom wrappers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
HAL events were also used for the shim driver's concerns
during the prototyping of API. Fix it now and use specific
shim driver events. That also allows new transfers to be
triggered from a single point.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add new USB device controller API and nRF USBD controller driver.
The new UDC API brings support for multiple instances and asynchronous
transfer model, transfers use net_buf and store methadata in the
user data area.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Set the inverted value of pixel format setting in MADCTL register to
current_pixel_format in display capabilities structure
if rgb-is-inverted enabled.
This make enables support for a module that mismatches the RGB setting
in the MADCTL register and the actual display color format.
(Such as Longan Nano built-in LCD module.)
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Implement a LED driver for Microchip XEC using the breathing,
blinking LED controller. The driver supports LED on, off, and
blink API's. The BBLED block uses the 32768 Hz clock domain
allowing the module to operate in light and deep sleep states.
Blink frequency is 32768 divided by 256 * (prescale + 1) where
prescale is a 12-bit value. Duty cycle is specified by an 8-bit
value where 0 = full off, 127 is 50%, and 255 is full on.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.
In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.
In particular this changeset is doing three things:
1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
`CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`
2. The cache API has been reworked.
3. Comments are added.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Re-enable the CAAM for entropy
now that the HAL driver has been fixed
Job descriptors must be accessed coherently
between CAAM DMA and core.
The M4 Cores still do not work
because of mpu/cache/kconfig arch complications,
disable caam for M4 cores in DTS
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
When pwm_it8xxx2_set_cycles() is called, we disable the pwm clock
at the beginning and enable it at the end, so there is a more than
1ms pwm low pulse when every time changing the cycle. The low pulse
would let some fans go to idle mode, so we don't gate the pwm clock.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Enable Zephyr device runtime power management mechanisms in Intel DMIC
driver. This allows Zephyr to track usage reference for power domain
gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch contains several small changes to the intel adsp power
domain.
- include missing header,
- replacing sys_write32/sys_read32 with sys_write16/sys_read16 since
DfPWRCTL is a 16 bit register,
- renaming struct to be more representing what it is,
- passing register address, not a value to the sys_read/sys_write
functions,
- pd_intel_adsp_init is now returning actual status.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
While diagnosing a problem on the STM32U585 in this function in
flash_stm32l5_u5.c, I had difficulty sussing out the flow of the
function and conditional logic.
This refactor seeks to improve clarity through a simplified flow control
using an early return to short circuit logic on subsequent calls to the
function and slightly more thorough comments.
Tested using tests/drivers/flash on the b_u585i_iot02a and in a
proprietary application and board which uses the STM32U585 and littlefs.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
In flash_stm32_page_layout, the FLASH_PAGE_NB macro is used to set the
page count in the flash layout returned to the caller. On STM32L5
platforms this is defined in stm32l5xx_hal_flash.h to be (FLASH_SIZE /
FLASH_PAGE_SIZE). However, on STM32U5 platforms the macro is defined in
the soc headers (such as stm32u585xx.h) define the macro as
(FLASH_BANK_SIZE / FLASH_PAGE_SIZE). This results in the flash layout
only reflecting the first bank on STM32U5 platforms with the maximum 2
MB of flash.
This commit resolves this discrepancy by directly calculating the number
of pages by dividing FLASH_SIZE by FLASH_PAGE_SIZE.
Tested on a proprietary board using the STM32U585 which mounts a
littlefs partition in the last 256 kB of its 2 MB of flash.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
Drop the async enable function. This feature is rarely/never used,
complicates driver design, and doesn't really follow the sync/async API
design/naming used in other areas. In the future we can introduce
regulator_enable_async if needed, with support from the driver class (no
onoff). Note that drivers like PCA9420 did not implement any
asynchronous behavior. regulator-fixed implemented in the past
asynchronous behavior using work queues, an overkill for most GPIO
driven regulators. Let's keep things simple for now and extend the API
when needed, based on specific usecases.
In the current implementation, reference counting is managed by the
driver class. \isr-ok attribute is dropped, since calls are potentially
blocking. Note that drivers like PCA9420 already violated such rule.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove regulator-fixed-sync specialization, create a single driver that
is always synchronous. The asynchronous part is rarely/never used, so
let's keep things simple for now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Do not set wifi optimizations by default in order
to free up IRAM room region. In case higher throutput
is necessary, one can enable this flags to optmize it.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
NXP S32 System Timer module includes a 32-bit count-up timer and four
32-bit compare channels with a separate interrupt source for each
channel. The timer is driven by the module clock divided by an 8-bit
prescale value.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
When configuring an LPSPI module for a new device with different baud rate,
the module needs to be disabled for the baud rate change to take effect.
This adds the necessary call to LPSPI_Enable before initializing the
module.
Fixes#51177
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
This casts the char * buffers to void * before giving them to the
LOG_DBG function to fix a warning at runtime.
Signed-off-by: Gaël PORTAY <gael.portay@gmail.com>
add Intel HDA DAI driver
Long device list in dtsi needs to be refactored in the future
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Remapping by default can confuse things that dynamically manage RAM,
such as newlib heap - since unused memory will be powered off by
default. So this patch shields this behaviour behind a non-default
Kconfig.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
pca9420_i2c.h has neem remamed to pca9420.h (device only has I2C, so
it's kind of redundant to have i2c in the header name).
pmic_i2c.h was again not generic but designed specifically for PCA9420.
All its macros have been renamed, s/PMIC/PCA9420, and moved to the
pca9420.h header.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Store all common configuration settings in the parent device. This
change should save ROM, since it avoids duplication.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The driver had a conceptual issue regarding current limitation. PCA9420
is able to limit the current flowing through VIN, ie input current. This
is a global setting, not individual to each regulator. This patch
creates a new DT property: nxp,vin-ilim-microamp to specify such limit.
It is applied when the device is initialized.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Voltage ranges were hardcoded in Devicetree, however, things can be
significantly simplified by using the recently introduce linear ranges
API. All values are now computed using information stored in the driver,
so there is no need to store any lookup table in ROM. Code should now
both be faster in average and consume less ROM.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Regulator registers were set for each BUCK/LDO in DT, likely because of
the way the devices were instantiated. When using a generic iterator,
ie, DT_INST_FOREACH_CHILD, there's no way to differentiate the child
being _parsed_. Since instantiation happens now based on child node
names, we are able to know which registers each devices gets assigned at
the driver level. This greatly simplifies Devicetree, and it actually
removes information that is not strictly hardware description from it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
