video_mcux_csi_init, which setups the CSI pins (i.e: calls
pinctrl_apply_state) was called after mt9m114_init which tries to do i2c
communication with the camera to read the chip id. But since one of the
CSI pins is the camera master clock, doing things in this order won't
work. This PR inverts the order in which the devices are initialized.
Signed-off-by: Michele Balistreri <michele@bitgamma.com>
The function to enable wakeup from deep sleep modes is not
available on all SoC's. Hence compile this only when the
wakeup_source property is enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Change init level of the mcux lpc dma driver to be
PRE_KERNEL_1 because some other hardware drivers
used on the same platforms as the lpc dma will be
dependent on the LPC DMA and are also initialized
in PRE_KERNEL_1, such as the Flexcomm UART driver
when using UART_ASYNC_API.
Therefore, remove k_malloc from init function and
make those variables statically defined instead of
heap allocated.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Some miscellaneous fixes to LPC DMA driver regarding status tracking:
- If a DMA channel has not been configured for any transfer,
there will be a bug caused by the virtual channel being -1
and then trying to index -1 into the driver data structs.
Add -EACCES return code to indicate this situation.
- Return -EINVAL from get_status if channel number is invalid
- Update the busy flag in the LPC DMA callback function.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Fixes for bug:
https://github.com/zephyrproject-rtos/zephyr/issues/57560
* don't do CCC if no i3c devices in device tree
* don't wait for MCTRLDONE status when issuing stop
* don't do data part of transfer if buf_sz is 0
* don't limit transfers to only i2c devices in the device tree
so "i2c scan" shell cmd works as expected
Signed-off-by: Mike J. Chen <mjchen@google.com>
Commit 246393e830
("drivers: spi: spi_nrfx_spim: Remove nrf_frequency_t handling")'
introduced two changes, one of them is removing the function
get_nrf_spim_frequency with a strange justification.
This change breaks support for peripherals written in a common way,
where the maximum frequency is set to the maximum supported
by the peripheral, not the controller, see shields for example.
On the occasion of bringing it back, the original function was
refactored to be easier to read and understand.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a USB device controller driver skeleton to use as a starting point
for implementing a specific driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
API function:
- `pl011_irq_tx_enable` is expected to enable and trigger TX interrupt.
Due to HW limiation, PL011 won't trigger TX interrupt if some data
wasn't filled to TX FIFO at the beginning. So that `isr_cb` must be
called at first time to enable TX irq.
- `pl011_irq_tx_ready` will return true when FIFO can accept more
data. Here we don't need wait TX FIFO to be empty.
- `pl011_irq_tx_complete` will return true when all data have been
sent from the shift register.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
A glitch was observed if a GPIO PIN was configured to a
non-default state by ROM and then Zephyr programs the pin
for the same configuration. Root cause is GPIO hardware
implementing two output bits for each pin. The alternate
output bit is in the pin control register and is r/w by
default. The other bit exists in the GPIO parallel ouput
register and is read-only by default. The hardware actually
reflects the pin's output value into both bits. The fix is
to configure the pin with alternate output bit read-write
and the last step is to disable alternate output which
enabled read-write of the parallel bit. GPIO API's can
then use the GPIO parallel out registers. Add logic to
return an error from the GPIO interrupt configure API if
a pin is not configured as an input. Hardware only performs
interrupt detection if the input pad is enabled.
Hardware supports a pin being configured for both input
and output. Applications should add the GPIO_INPUT flag
to all pin configuration requiring interrupt detection.
The interpretation of input and output flags for the
get configuration API appears to be only one of the
flags can be set. Please refer to the GPIO driver tests.
Updated GPIO interrupt configure to clear the input pad
disable bit due to interrupt detection HW is connected
only to input side of pin.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Bug 1: Fix lsm6dsl_gyro_set_fs_raw does not clear FS125 to register when
setting the full range to be other values.
Bug 2: Fix lsm6dsl_gyro_channel_get does not use the current
gyro_sensitivity when getting data from the gyroscope.
Signed-off-by: Jackie Yang <jackie@jackieyang.me>
Several sections of the STM32 ADC driver are #ifdef by a combination of the
same SOC defines that share similar IPs. These are F2/F4/F7/L1, and
F1/F37x.
Each of these combinations is now replaced by a specific compatible, which
makes the code a bit lighter and more succinct.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add ifdef around some functions that don't exist for STM32F37x (ADC_V2_5)
like it is done for STM32F1x.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Inverts the logic of some #ifdef, replacing lists of newer series by a
list of NOT older series. This makes it shorter, and more future-proof as
future series are more likely to work out of the box, without need to
manually add a new define in each place.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some STM32 families that need to check the ADRDY flag after enabling the
ADC were not doing it. The #ifdef has been updated to fix that.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fix a compilation error for the ethernet driver smsc91x that
prevents the build with asserts enabled.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
This commit adds BLE support to the `efr32xg24_dk2601b` board. It also
modifies the SiLabs BT HCI driver to accomodate the EFR32xG24 SoC
series.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
BDCR and PWR_CR could be required for LSE or RTC for instance.
Enable it here as for now, no sophisticated PM handling is available
on F0 and F3 series.
Fixes#56449
Fixup for #56505
Signed-off-by: Kay P <kayo@illumium.org>
rx_thread() is started by eth_initialize(), while dev_data->iface is
populated by eth_iface_init() (called by net_init()).
Usually eth_iface_init() has completed by the time rx_thread() hits its
idle timeout and accesses dev_data->iface, but in case of a time-intensive
SYS_INIT item between eth_initialize() and net_init(), this is not
necessarily the case, causing a NULL dereference. This can be forced by
putting a k_sleep(K_SECONDS(5)) at the top of eth_iface_init().
Start rx_thread() in eth_iface_init() instead (which runs after
eth_initialize() due to init priorities) to make sure everything is
initialized properly.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Allows Ethernet communication between "cells"
in the Jailhouse hypervisor.
The vring queue deviates from a standard virtqueue
so is implemented separately.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This allows finding the correct PCIe device when multiple devices
have the same vendor-id/device-id but differ in the class-rev register
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Driver init should be using instance based macros,
not nodelabels numbering, there is no guarantee
about which nodes will be assigned which instance numbers.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add Kconfig guards for CONFIG_CAN_MAX_STD_ID_FILTER and
CONFIG_CAN_MAX_EXT_ID_FILTER as they only apply to the STM32 bxCAN driver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove the STM32H7 specific Kconfig overrides for setting the maximum
number of standard and extended CAN RX filters as they are unused.
The number of available standard and extended filter elements for Bosch
M_CAN can be configured via the devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The SSD16xx driver used to use the SCREEN_INFO_DOUBLE_BUFFER flag to
indicate to the LVGL integration that it needs writes to be performed
twice. This was required because partial writes require both the old
and new buffer to be written.
This behavior is really an implementation detail and only applies to
partial refresh. Do this buffer maintenance in the driver instead.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Remove the optional call to ssd16xx_update_display() in
ssd16xx_clear_cntlr_mem(). This doesn't really belong in that function
and just adds a non-obvious boolean argument to the function.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update the device tree bindings for the SSD16xx driver to make it
possible to specify multiple refresh profiles.
The only profile currently supported is the 'full' profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently provides basic support for most chips in
the Solomon Systech SSD16xx range of e-paper drivers. We currently use
the SSD1608, SSD1673, SSD1675A, and SSD1681 in various boards
supported by Zephyr.
The main user-facing difference between the various SSD16xx chips is
the resolution they support (sources & gates), but there are other
differences as well. For example:
* 8 or 16 bits used to represent x coordinates
* 8 or 16 bits used to represent y coordinates
* Differences in refresh configuration (SSD16XX_CMD_UPDATE_CTRL2)
* Differences in LUT sizes
The driver currently assumes that the user specifies the number of
bits used to describe coordinates. However, as we add support for more
chips, more of the differences will become apparent and need
workaround.
Comparing data sheets from different chips in the SSD16xx range
suggests that there are (at least) two different generations
present. These differ in the size of the LUTs they expect and the way
they handle partial refresh. This impacts register layout where
SSD16XX_CMD_UPDATE_CTRL2 uses bit 3 selects "mode 2" whereas older
devices uses this for a mode referred to as "initial".
In order to add support for partial refresh in newer devices, we need
to be able to distinguish between the different generations of the
chip. It might be possible to add a DT property to indicate the
revision, but that seems like a bit of an anti-pattern and it would be
hard for users to specify the correct chip generation.
This change introduces chip-specific compatible strings instead of the
generic SSD16xx. There is unfortunately clear pattern that can be used
to distinguish different generations, so the full chip name must be
specified. A benefit of this is that we don't need to specify the
width of the fields describing coordinates in device trees.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Only UVB_EVT_REQUEST type passes the pkt argument.
This was overlooked in the last refactoring and
resulted in a zero pointer dereference.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
LSM6DSL's datasheet [1] lists 1666, 3332 and 6664 as valid ODR values for
accel and gyro. Update those from 1660, 3330 and 6660.
[1] http://www.st.com/en/mems-and-sensors/lsm6dsl.html
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Commit e015c00300 ("sensor: add lsm6dsl sensor driver") that introduced
initial support for lsm6dsl used 245dps instead of 250dps. According to
referenced documentation at [1] the latter is correct.
Use value of 250 instead of 245 for gyro range.
[1] http://www.st.com/en/mems-and-sensors/lsm6dsl.html
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
