There are some issues with the extended endpoint settings. The incorrect
setting leads to the chip being unable to respond with NAK when the host
polls the extended endpoint for data transfers. Additionally, the controls
for the extended endpoint's ISO and PID data sequence are also incorrect.
This commit addresses these issues to properly support extended endpoint
transactions.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
There are two registers that control the selection of one FIFO as data
buffer for 15 endpoints (ep1-ep15). Both registers should be configured
before sending and receiving data. Additionally, there was an issue with
the corresponding FIFO index setting in the 'usb_dc_ep_read_continue'
function, which has been addressed in this commit.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Turning on clock via clock controller and
resetting PIO device via reset controller on initializing.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Turning on clock via clock controller and
resetting PIO device via reset controller on initializing.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Turning on clock via clock controller and
resetting ADC device via reset controller on initializing.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Changed how to get clock frequency for PL022
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Removed all function calls from Raspberry Pi Pico SDK
Added functions for setting uart baudrate and format
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Changed how to get xtal frequency for Raspberry Pi Pico
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The stm32H5 mcu has an independent USB supply to be enabled
at init with LL_PWR_EnableVDDUSB function like the stm32U5 serie.
Both series have PWR_USBSCR_USB33SV bit in their USBSCR POWER reg.
and other series all have PWR_CR2_USV bit in their CR2 POWER reg.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Boot into the deep power down state when `SPI_NOR_IDLE_IN_DPD` is not
enabled. DPD is the correct hardware state for the `SUSPENDED` software
state. Without this change, it takes a cycle of
`SUSPENDED->ACTIVE->SUSPENDED` to get to the low power state.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The previous behaviour led to an issue where we already expected data1
on the first transfer instead of data0. The DesignWare USB DC actually
implements the same behaviour. Also, the next_pid flag has to be reset
on setting up the endpoint.
Fixes#66283.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
The driver right now re-enters polling mode a couple times after the
matrix has been detected as stable as the key interrupt is still pending
and fires again once detection is reenabled.
Clear pending WUI interrupts before reenabling key press detection to
avoid that.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Information about IOAPIC can be located not in the first
DMAR Hardware Unit Definition subtable. Iterate them all.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Fixes uninitialized variable return by returning zero
at the end of function.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This code fixes following issue:
The TX data chunk (with NORX set) is send to chip (via SPI) and at the
same time a frame is received (by the LAN8651 chip), there will be no IRQ
(the CS is still asserted), just the footer will indicate this with the
rca > 0.
Afterwards, new frames are received by LAN865x, but as the previous footer
already is larger than zero there is no IRQ generated.
To be more specific (from [1], chapter 7.7):
----->8-------
RCA – Receive Chunks Available
Asserted:
The MAC-PHY detects CSn deasserted and the previous data footer had no
receive data chunks available (RCA = 0). The IRQn pin will be asserted
when receive data chunks become available for reading while CSn is
deasserted.
Deasserted:
On reception of the first data header following CSn being asserted
------8<------
Doc:
[1] - "OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface"
OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The description is a bit misleading as the packet is not even read in
the mentioned case by the OA TC6 Zephyr driver.
When the timeout occurs the data (packet) received by LAN865x may be:
- Read latter if still in the RX buffer of LAN865x
or
- Is (probably) dropped by LAN8651 itself as the RX buffer gets overrun
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The parity of the received footer from data transfer (also including the
NORX) shall be checked before members of struct tc6 are updated.
This prevents from updating the driver's crucial metadata (i.e. struct
oa_tc6) with malformed values and informs the upper layers of the driver
that error has been detected.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
With the current approach, the driver prevents from TX transmission
when waiting on timeout (standard 100ms) for available memory to be
able to allocate memory for RX packet.
It is safe to just protect the part of reading chunks. In that way
pending TX transmission can be performed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
If the DT node for mdio of nxp enet has a mdc freq specified,
use this when configuring the module.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
In init function, start timer with period CYC_PER_TICK if tickless is
not enabled, This change is for fixing the issue that disabling
CONFIG_TICKLESS_KERNEL the OS tick is not work issue, this
causes the OS not starting scheduling correctly.
Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
This commits create the dts binding for Ambiq BT HCI instance.
And create the SPI based common HCI driver for Ambiq Apollox
Blue SoC and the extended soc driver for HCI.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Fix a possible race condition in the keyboard matrix library where a key
would get pressed between the last read and reenabling the (edge
sensitive) interrupt and the even would be lost.
The window for this to happen is very narrow and had to artificially add
a sleep to reproduce it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change the interrupt setup from both edge to edge to active. Edge to
active is all was needed anyway and it makes this compatible with gpio
controller that only support single edge interrupt.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a device driver to read events from a Linux evdev device node and
inject them back as Zephyr input events.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The driver currently supports only dedicated FIFO mode (with
dynfifosizing if enabled). Control, bulk and interrupt transfers are
supported, isochronous transfers are not yet supported. The driver
accesses controller registers using sys_io.h, but for debugging purposes
one can get a register map from the driver's config, similar to the
usb_dc_dw.c driver.
Initial support also has vendor quirks for the STM32F4 SoC family.
Tested on NUCLEO-F413HG.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Use new common header and remove usb_dw_registers.h.
No functional changes, only renaming of registers and field identifiers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This header is based on drivers/usb/device/usb_dw_registers.h and
describes registers of the DWC2 controllers IP and is intended for use
in both device controller drivers and a host controller driver. The
difference to usb_dw_registers.h is that this header does not confuse
offsets with bit positions, contains all the definitions required for
device mode, has register and bit field names identical to the databook
and no annoying underscores.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
If GDBSTUB is enabled and the kernel runs in tickless mode, the timer
must not convert the delta cycles to a 32-bit data type (cycle_diff_t in
this case). The delta_ticks variable would overflow and the next timeout
would be set before the current timestamp, thus generating an interrupt
right after leaving the handler. As a result, the system would receive
tens of thousands of interrupts per second and would not boot.
Cc: Michal Sojka <michal.sojka@cvut.cz>
Signed-off-by: Marek Vedral <marek.vedral@gmail.com>
rtc_get_time() on STM32 does not implement the -ENODATA return code.
This prevents testing the initialisation status of the RTC.
Fixed by reading INITS flag and adding a error path in
rtc_stm32_get_time().
Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>
This reverts commit bffa0c6bddbc91d39f4b01baa34e3d0595760d50.
This FIFO implementation causes a regression by which the SPI
peripheral generates several spurious SCK cyles after the last
data has been sent.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
