Add support for clock subsystem configuration and pinctrl in the
DesignWare I3C driver to enable proper clock control and pin
management on platforms that require them.
Changes include:
- Add clock_subsys field to dw_i3c_config structure.
- Update clock_control_get_rate() and clock_control_on() calls to use
the configured clock subsystem instead of NULL.
- Use COND_CODE_1 with DT_INST_PHA_HAS_CELL to conditionally extract
clock subsystem ID from devicetree, providing backward compatibility
for platforms without clkid cell.
- Include pinctrl-device.yaml in devicetree binding to enable pinctrl
support for platforms that need pin configuration.
- Gracefully fallback to NULL behavior when clkid is not specified.
This follows the same pattern used by other I3C drivers (mcux, renesas_ra)
and enables proper clock management for SoCs that require clock subsystem
identifiers while maintaining compatibility with existing devicetree
configurations.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
The I2C target implementation for i2c_dw does not follow the
zephyr target specification. The following three issues are corrected:
1) The read_requested CB is called on every byte of the transaction
- it must be called only on the first byte of the transaction
2) The read_processed CB is called on every byte of the transaction
- it must be called only on bytes following the first byte
3) Bytes returned in the data ptr param of read_processed are not
sent to the controller
-These bytes must be sent to the controller
Signed-off-by: James Growden <jgrowden@tenstorrent.com>
This is a follow-up to commit cafa288197.
Bit masks should use the bitwise OR operator, not the logical one...
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The fast wake feature in the MSPM0 GPIO peripheral allows the GPIO module
to stay in a low-power state and detect interrupt events on the device pins
without requiring a high-speed clock. This allows the device to support
fast wakeup from low-power modes, such as STOP and STANDBY, on any GPIO
pin.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Extend vpr_launcher and device tree bindings to support configuring
the DMA secure attribute.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
This change makes improvements and bug fixes for the Infineon PWM
driver. These include:
* Removes hard coded register addresss from driver.
* Addresses issues causing pwm_api and pwm_gpio_loopback tests to
fail, as well as functional failures.
* Restructures device tree file to better represent the hardware
architecture of the tcpwm module.
* Allows configuration of hardware behavior when PWM is disabled.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
* Changes driver naming to reflect hardware IP being used (TCPWM)
instead of referencing cat1. Cat1 is an internal infineon
reference which has little meaning to users and is being phased
phased out.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
flush pending irq before enableing the irq.
In the litex soc, if an irq is not enabled, it will
it can still be registered and will be pending
if it occurs, it will just not be send to the cpu
until the irq is enabled.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
When Octal IO mode is to be used with DDR in mx25u family chips,
bit 1 instead of 0 must be set in the Configuration Register 2 at
address 0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for supplying power to the flash chip by activation of
a GPIO specified through the "supply-gpios" property. Implementation
of gpio_reset() is also slightly modified so that it is consistent
with soft_reset() and the new power_supply() and so that all these
functions can use a common routine that performs a reset recovery
delay.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Using a GPIO reset for a flash chip that has a dual function pin
(RESET# or SIO3) and is to be used in Quad mode is rather a bad idea
and so is clearing of the Quad Enable bit at every initialization
of the flash driver, since this bit is usually non-volatile, so such
operation means unnecessary wearing of the flash chip. Soft Reset
should be use instead in such case.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add implementation of the most common Soft Reset routine (sequence of
reset enable instruction 0x66 and reset instruction 0x99).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Complete implementation of quad_enable_set() by adding support for all
possible Quad Enable Requirements (QER) as specified by the SFDP JEDEC
standard (JESD216). Add also corresponding octal_enable_set() to handle
Octal Enable Requirements.
Also remove initial waiting from mxicy_mx25r_post_switch_mode() which
became unneeded, as now such waiting is done in cmd_wrsr() which is
called at the end of quad_enable_set().
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Use standard operation codes and parameters from SFDP for handling
the used flash commands (allow to override some of them through dts
with the `read-command`, `write-command`, and `rx-dummy` properties)
- Use all available erase types as specified by SFDP
- Allow using all IO modes
- Add support for switching to 4-byte addressing mode
- Use common functions for reading and writing of status registers
and for enabling write operations
- Switch IO mode (between the target one and Single IO) in a common
function that performs transfers and do it only when required for
a given command
- Make checking of JEDEC ID at initialization optional
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Get parameters for used flash commands and requirements for enabling
Quad and Octal modes from dts uint8-arrays containing data read from
SFDP tables for particular flash chips.
Also introduce `pre_init` quirk that allows alteration of the above
parameters or complementation of them in a specific way for particular
flash chip families.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Define a video device for each pipe instead for the main dcmipp device
since the pipe is the device that communicates with application
(zephyr,camera chosen node), not the dcmipp device.
This helps to enable camera controls as well.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The pipe nodes are not video interfaces. Describe them as normal child
nodes instead of using port/endpoint.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The missing variable "config" in phy_mc_ksz8081_cfg_link() maybe
used by the macro "USING_INTERRUPT_GPIO", add the variable to avoid
compiling errors.
fixes: #95492
Signed-off-by: Tony Han <tony.han@microchip.com>
Asynchronously release the device after a small delay to minimise power
state transitions under multiple sequential API calls (e.g. NVS).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Request calibration of the ADC in the voltage divider driver to improve
the accuracy of the measured voltages.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Adopt new sys_count_bits helper from util.h and avoid
having conflicting definition
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Add possibility of using data strobe signal (DQS) called RXDS in
the SSI documentation. This signal may be necessary to make use
of DDR modes.
Remove also a TODO comment that should have been removed when support
for DDR was added in fc64fec8fe.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Within spi_rtio_copy there'd be a case where the tx_buf pointer would
mistakenly get assigned the address of an rx buffer.
Specifically this would happen in the case where there are no rx buffers
provided, and as such this would lead to pontential nullptr dereferences.
Correct the mistake to let tx_buf correctly point to the provided tx
buffers.
Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
I3C targets can join the bus after initialization so CCC should not exit
if no known I3C devices exist at init time.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The sensor interface gives current channel values in Amps, but the "I"
(current) value is displayed in mA, so needs to be converted accordingly.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
Add scmi_cpu_set_irq_mask function for scmi nxp cpu driver,
set cmc wakeup mask from scmi interface by this.
The CPU_IRQ_WAKE_SET is sent to the scmi platform
to determine which interrupt can wakeup the cpu platform
when the corresponding interrupt occurs
"1" means the IRQ cannot wakeup CPU platform
Each bit corresponds one-to-one with the interrupt
controller of the platform such as nvic in mcore
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Fixes the `spi_loopback` test failure on board Renesas `rzg3s_smarc` since
the test has been updated by zephyrproject-rtos/zephyr/pull/86383
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Fix to ensure temperature is sampled at the same timestamp as x,y,z axis
data.
Signed-off-by: Vinayak Sunilkumar Priyadarsini <Vinayak.SunilkumarPriyadarsini@analog.com>
As the other spi_nxp_lpspi driver source files use DT_DRV_COMPAT
and that is used to determine in spi_context.h if the gpio cs
code is used, it also have to be defined in spi_nxp_lpspi_common.c
so there is no mismatch and breaking of the driver.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Added support for combined write-read operations
with repeated start for asynchronous (async)
operations in the Silabs I2C driver for EFR
series 2 devices.
Signed-off-by: S Mohamed Fiaz <Fiaz.Mohamed@silabs.com>
Invert the RX/TX checksum offloading to hardware behaviour so that
hardware checksum generation / evaluation for TCP/UDP packets on
either IPv4 or IPv6 is enabled by default, but can be disabled
explicitly.
This behaviour, which should optimize network performance, has
become possible with the implementation of the device driver's
get_config function, indicating to the network stack that HW
checksum offloading is not supported for, e.g., ICMP packets.
Before this implementation, enabling the HW checksum offloading
resulted in invalid packets for any unsupported protocol and
could therefore not be enabled by default.
For QEMU, which does not support the emulation of the HW
checksum offloading, automatically disable the offloading.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
For clear, this splits large isr function into smaller ones which are
dedicated for handling plug/unplug, wakeup, reset/suspend/resume, SOF,
Setup, and endpoint events.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
This refines interrupt handling sequence: clear interrupt flag first,
then process it. This can avoid one race condition when interrupt flag
is cleared but not processed for interrupts of the same type coming
very closely.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
