The UDC stack assumes that 'halt' on control endpoints is automatically
cleared by device drivers and never calls udc_ep_clear_halt() for such
endpoints. In practice, most controllers do perform this automatic clear
in hardware, but this requires special handling in udc_ep_set_halt() for
control endpoints (EP0), as setting the 'halted' bit on such endpoints will
lead to the software getting out-of-sync with the hardware.
Update the UDC skeleton driver to handle this edge case and add a comment
documenting the stack's behavior, along with the hardware behavior expected
by the code added to the skeleton driver for it to be functional.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Mathieu CHOPLAIN <mathieu.choplain-ext@st.com>
Explicitly configure retention mode when powering up HPSRAM banks to
ensure consistent behavior across hardware platforms.
After D3 power state transitions, the retention mode configuration can
become undefined due to hardware reset. This causes test failures in NVL
FPGA testing environment where the hardware strictly enforces retention
mode settings.
The fix ensures retention mode is properly set in two locations:
- sys_mm_drv_hpsram_pwr(): Configure retention mode for all bank
power-up operations
- adsp_mm_restore_context(): Explicitly set retention mode during
D3->D0 restore sequence after each bank is powered up
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The SAMC21 has a different revision of the DAC peripheral.
This change adds an ifdef to handle the changed SYNCBUSY register.
Signed-off-by: Stefan Giroux <stefan.g@feniex.com>
added logic to determine the direction of USB transfers for non-setup
packets using the endpoint direction. This ensures proper handling of
USB_IN and USB_OUT directions.
Signed-off-by: Richard Yim <richardyim@ami.com>
The timer is enabled before comparison value is set, which can lead to
unexpected behavior if the registers contain uninitialized values.
Should call arm_arch_timer_enable() after arm_arch_timer_set_compare().
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Plan to restructure eth_stm32_hal into two files, eth_stm32_v1
and eth_stm32_v2, while retaining the git history of v2.
Signed-off-by: WenBin Zhang <freey7955@gmail.com>
Split the codes of v1 and v2.
V1 supports F1/F2, while v2 supports F4/F7/H5/H7/N6.
This makes it easier to understand and add new functions.
Signed-off-by: WenBin Zhang <freey7955@gmail.com>
Add support for the Renesas RA Direct Memory Access Controller,
including driver source files, Kconfig options, and DTS bindings.
- Add initial implementation of the RA DMAC driver
- Add dedicated Kconfig and CMake integration
- Provide Devicetree bindings for the RA DMAC
- Update module Kconfig to include the new driver
This enables DMA functionality on Renesas RA series MCUs.
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
MAX32 UART's "almost empty" fires when the FIFO gets down to one byte, but
when sending just one byte, no interrupt is raised, resulting in stalled
TX. Use a timer to ensure the ISR is invoked and TX processing continues in
that scenario.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Some applications need to throttle RRAM writes to handle peak current
management.
Add CONFIG_NRF_RRAM_THROTTLING_DATA_BLOCK which defines the maximum
chunk length that can be written at once.
Add CONFIG_NRF_RRAM_THROTTLING_DELAY which configures the sleep delay in
microseconds after each write.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
The jedec-id cannot be read after flash device is set to octal mode.
Fixed by moving the jedec-id comparison to
flash_flexspi_nor_check_jedec() which already reads the jedec-id when
flash device is still in single spi mode.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
This adjust the MAC CONFIGURATION register settings to 10MBit/s if needed.
The reduction is needed for 10MBit only PHYs.
Signed-off-by: Adib Taraben <theadib@gmail.com>
Forward get/set selection to the camera source and update the driver's
video_format on set so buffer sizing and streaming follow the selected
region.
Signed-off-by: Armin Kessler <ake@espros.com>
Add I2C_TARGET_ALLOW_POWER_SAVING config. Enable this config makes I2C
target device can enter Doze/Deep doze states while the bus is idle.
Ongoing transfers will block low-power entry until they are completed,
ensuring correct communication while still reducing overall power
consumption.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
DSA is part of Ethernet and will utilize more Ethernet definitions for
more features support. So, it's proper to let DSA header include
Ethernet header with moving some DSA definiton from DSA header to
Ethernet header and adding DSA header including in c files using DSA
definition.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
remove unneeded soft irq, as disabeled irqs
will still be registered, but just not propagated
to the cpu until it is enabled again.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
I manually checked the errata sheets for all STM32Hxx/STM32Uxx parts to
confirm the defect's presence or absence. It appears to have been resolved
in silicon on newer parts (e.g., STM32U3xx family), so hopefully this test
will not need grow further (knock on wood).
Co-authored-by: Nicolas Zuluaga <nicolas.zuluaga@rbr-global.com>
Signed-off-by: Samuel Coleman <samuel.coleman@rbr-global.com>
Update ethosu_flush_dcache() and ethosu_invalidate_dcache() to accept
base_addr and base_addr_size arrays, with num_base_addr as the element
count, as required by the new Ethos-U driver. Add (uintptr_t) casts to
support 32-bit targets.
Signed-off-by: Johan Alfvén <johan.alfven@arm.com>
Some devices supported by this driver do not have a write-block-size
of 1 such as the mt35xu01gbba. This value is assigned in the dts and can
be used instead.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Counter RTC driver is written using the counter API as a
target instead of a hardware. It can adapt to all RTC
device without broken-down time register but with counter.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The ws2812_spi driver supports both a fast path for 8-bit symbols and
a generic path for other sizes.
This change introduces a devicetree-based, build-time check to
determine if all enabled instances use 8-bit symbols. If so, the
generic path logic is removed from the build.
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420
(semi)planar formats which can be output by the main #1 pipe.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
ISP is part of the pixel pipes hence it doesn't make any sense to
try to call ISP external handlers if the DCMIPP doesn't have pixel
pipes available.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The maximum frequencies for SYSCLK, AHB and APB bus have changed since
the first issue of the datasheet. Setting values according to the up-
to-date datasheet.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Add a UART driver for the VIRTIO console device.
This driver has support for both polling- and interrupt-based i/o,
as well as interacting with up to 32 console ports (disabled by
default). Based on the Xen HVC driver.
Tested with the console subsystem sample programs. Aside from
enabling CONFIG_PCIE, setting CONFIG_HEAP_MEM_POOL_SIZE to a
high enough value (for example 100000) is necessary -- as is done
in the virtiofs sample.
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
This fixes:
* if-statements that check whether a given bit lies within
specification-defined ranges
* a behavior in virtio_pci.c -- where it would read feature bits
from the device and write them back whenever the user tried to
set their own -- which led to bugs
* struct virtio_pci_common_cfg, adding two new fields, bringing
it in line with the specification; the entire struct definition
was reformatted as following the existing style would trigger
warnings
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Use DIV_ROUND_UP to ensure listen_interval is rounded up instead of
being truncated during division by the beacon interval.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
In the Japan regulatory domain, channel 14 is restricted to
802.11b/g operation and does not support HT (802.11n) capabilities.
Disable HT capabilities when operating on channel 14 in AP mode.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
Fix stm32 XSPI driver to restore the bus command concurrent access
protection that was mistakenly removed on memory mapping operation
by commit e5620e07c9 ("drivers: flash: stm32 xspi flash read with
memcopy when executing").
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
- Add ``R_BSP_SecondaryCoreStart`` for the primary core to start
the secondary core
- Disable ``clock_init`` for the secondary core
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
