data->rtc_base is not being used anywhere while data->rtc_registers is
only used as a temporary variable. Remove them from the driver.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
UART_RX_RDY event can be generated from UARTE interrupt or k_timer
handler. When ENDRX event occurs then k_timer is stopped (it can
be restarted if there is another buffer provided). However, if UARTE
interrupt priority is higher than k_timer priority (RTC is used
underneath) then k_timer handler may still be executed later.
K_timer notifies new bytes based on RXDRDY HW event which is
counter by the TIMER (using PPI). It may happen that RXDRDY
event arrives due to byte received into RX FIFO but since there is
not buffer provided it stays in that FIFO. Given all this, it
was possible that RX_RDY event was reported from ENDRX UARTE event,
timer was stopped but because UARTE interrupt had higher priority
timer handler is executed after UARTE interrupt is handled. In
timer handler TIMER counter reports more bytes and calls
UART_RX_RDY event with null buffer and non-zero amount of bytes.
Fixed by generating UART_RX_RDY event only if RX buffer is not
null.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
No need to check if an uint8_t is greater or equal 0 in
lp50xx_set_brightness.
Fixes CID 322654
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The reference document says that the formula for negative
temperatures has two minus signs missing.
fixes#68710
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
The point of this commit is to allow users to request specific
channels. The following code snippet shows how this may now be
achieved:
int requested_channel = 5;
int ret = dma_request_channel(dev, &requested_channel);
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
After #63289, multi-level interrupts are now encoded using
macro magic. This means that using the generic DT_INST_IRQ_BY_IDX()
to fetch the INTID is no longer an option as the queried INTID
will be the one specified through the node's `interrupts`
properties. To fix this, switch to using DT_INST_IRQN_BY_IDX()
which will return the correctly encoded INTID.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, the number of channels supported by the controlled
is computed based on the size of the channel array. This
works well only if there's no gaps (i.e: "dma-channels" property
is used or "valid-channels" property is used with contiguous
channels) but will break if there are any gaps. For instance,
if the user wants to use channels 16 and 17 and specifies them
through the "valid-channels" property, they won't be allowed
to do so because dma_request_channels() will stop at channel 1.
As such, to fix this, simply use the number of channels from
the HAL configuration which is the maximum number of channels.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
If the channel suspend with draining fails on stop because of reasons
outside of the scope of the DMA driver (the peripheral is powered off
before trying to drain for example) we must continue and disable the
channel.
The channel can be released by the client despite of it remained enabled.
A new DMA channel request can pick the channel (as it is released) but
re-configuration is going to be skipped and the use of the channel is going
to fail. Then we will see the same drain timeout on channel stop again
since the channel retained the configuration which resulted the first
timeout.
The drain timeout was made fatal by an earlier commit which fixed the
WAIT_FOR return value handling.
Fixes: 6226f9e6e4 ("dma: dw: fix the return value check")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The driver masked the return value of a pin read operation before
checking the error.
Thus not detecting a potential error and leading to logically
dead code, which was detected by coverity in CID 340853.
Anther instance XORs 1 before returning, resulting in an unexpected
return value;
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The res param in offload_freeaddrinfo is not used.
Mark it as unused, to avoid static analysis complaining about
Parse warning (PW.PARAM_SET_BUT_NOT_USED)
Fixes CID 316235
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
uart_emul_fifo_read() didn't regard the size arg, hence if the RX ring
buffer contained more data than the size of the input rx_data buffer
size, this could result in buffer overflow. This becomes more obvious
when configuring device tree property latch-buffer-size > 1.
Signed-off-by: Andreas Anderberg <andreas.anderberg@u-blox.com>
This reverts commit 780b12854c.
"drivers: ieee802154: nrf: cache radio channel"
Implementation affected RCP devices in openthread as MAC layer
does not call `Receive()` functions after transmit is done.
Additionally, after sending a frame to a new channel (for example
while discovery operation), radio switches to RX state immediately
after TX, but continues to listen on old channel for about 5ms,
until MAC layer calls `Receive` operation, forcing to change the
channel.
Signed-off-by: Maciej Baczmanski <maciej.baczmanski@nordicsemi.no>
This CL updates the event data returned by espi_reset.
Return 0 for eSPI bus in reset, and 1 for eSPI bus out-of-reset.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
First, the API ops are available only if
CONFIG_UART_USE_RUNTIME_CONFIGURE=y, but the driver was not guarding the
code. Also, according to the API specs, these functions are optional,
and the interface already returns -ENOSYS if they are not implemented.
To solve both problems, just drop the dummy implementation.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Systematically enable the UART clock again when exiting a low power mode
before reading the UART register.
Even though the previous code worked on STM32WBA, for most series, it is
necessary to enable the clock to access the registers, otherwise they read
as 0.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
info level is printed always to console and it's noisy.
Change to debug level, which can be enabled with
CONFIG_MODEM_MODULES_LOG_LEVEL_DBG
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Whenever UART_RX_DISABLED event is received module attempts to
re-enable receiver since in interrupt driven API receiver is
always on. However, it is possible that there is no free buffers
and in that case attempt to enable the receiver will fail with
-EBUSY. That scenario shall be accepted since the receiver will
be re-enabled when at least one buffer will be freed.
Given that, -EBUSY return shall be accepted (no assert) and
number of pending RX buffer requests shall be reset only on
successful enabling.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
return value of pwm_rpi_get_clkdiv contains implicit conversions
from 'float' to 'double', triggered by floating-point operations
involving mixed data types.
Signed-off-by: Jannis Ruellmann <j.ruellmann@kunbus.com>
Commit b2eaa6448076 ("drivers: dma: intel-adsp-hda: add delay to stop
host dma") added a wait on GBUSY state to host DMA stop.
This is problematic as in some case (like SOF chain-DMA usage),
the host DMA side RUN bit is not cleared when intel_adsp_hda_dma_stop()
is called. It is not possible to wait on GBUSY bit as there are
valid cases where it can remain set.
Address the original problem described in SOF bug #8686 and add a
polling check for intel_adsp_hda_is_enabled(). As per the bug
description, in some cases the GEN/FIFORDY bits are not cleared
immediately and if a new call to intel_adsp_hda_dma_stop() is made, the
PM refcounting will go haywire.
Link: https://github.com/thesofproject/sof/issues/8686
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The CST816S chip ID have an alternative value. It seems that this
field represents in fact a version number of controller. Fix by adding
the new chip ID.
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
Fix coverity integer handling issue (CWE-188).
Modifying a variable through a pointer of an incompatible type (other
than unsigned char) can lead to unpredictable results.
Fix: #67965
Coverity-CID: 248434
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Using the 8 base clock cycles per bit period setting (instead of 16)
reduces the uart baud rate error when using a 12MHz crystal (found on
many RA Microcontroller development kits boards). This setting also
slightly reduces the error when using the internal 48MHz oscillator,
used by the Arduino UNO R4 Minima board currently support by Zephyr.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
With the device_sync_sem semaphore, there is the possibility of
the code not returning to give it back
(mcux_flexcomm_master_transfer_callback is never called),
causing it to get stuck in k_sem_take(&data->device_sync_sem, K_FOREVER)
in subsequent calls.
The i2c driver recovers by other means
(enabling FSL_FEATURE_I2C_TIMEOUT_RECOVERY)
but the callback might not return.
Adding a timeout option allows for this occurrence to be avoided.
Signed-off-by: Guilherme Casa Nova <guilherme.casa_nova@dell.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Check the return code of mipi_dbi_reset, and do not delay for the reset
wait time unless the mipi controller has issued a hardware reset to the
display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix usage of MIPI buffer descriptor in ili9xxx driver. Previously, the
buffer descriptor size was being set to display buffer size. For cases
where the write height/width was not equal to the size of the buffer, this
resulted in additional data being written that was not needed. To
resolve this, calculate the mipi descriptor buffer size in the driver
Also, remove the unconditional setting of mipi_desc.height, as this
would override the previous (correct) setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a custom driver that takes care of loading and launching RISC-V VPR
cores found on the new nRF54 SoCs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
... in the related parts, so that the driver can be used on nRF54H20
where the clock control is not present yet.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On nRF54H20, only the new shim can be used and the enhanced poll out
cannot be enabled since there is no DPPI support for this SoC yet.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Move code that prepares `NRFX_CONFIG_GRTC_*` definitions based on
information from devicetree from the nRF54L15 nrfx_config header
to the global one, so that the code can be used by nRF54H20, too.
The checks that validate owned-channels and child-owned-channels
DT properties are moved to the nrf_grtc_timer driver so that
the global nrfx_config is not polluted unnecessarily.
The default values in nrfx_config_nrf54l15_enga_application.h
are restored to those from the corresponding template file.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds new NXP mailbox driver for MBOX device.
NXP mailbox IP driver supports sending data between cores.
It uses 32 bit register to trigger irq to other core.
This driver implementation uses 4 bits for channel selection of
triggering mode, 4 bits for channel selection of data transfer and
rest 24 bits for data.
NXP mailbox IP Reference Manual UM11126, Chapter 52.
https://www.nxp.com/webapp/Download?colCode=UM11126
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Address and size are given by the DTS register property
of the qspi nor : to be used by the qspi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor : to be used by the ospi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add power management support to the gpio-qdec driver.
This is a bit complicated by the fact that the driver has two modes of
operation and the interrupt, timer and idle work ineract with each
other.
The suspend sequence is:
- set the suspended bit (inhibits the poll timer so that it does not
resubmit the idle work)
- cancel the idle work (so that it does not schedule and re-set the
interrupt or timers)
- disable interrupts (if used)
- stop the sampling timer
- disconnect the pins
The resume sequence is more or less the opposite.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Some devices like S32K1xx don't feature an internal 32.768 KHz
oscillator. Also, updated the code to use the existing HAL API
for this purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
