Adding a hook for tests to inject a mock transport and migrating the
accel test to test bmi160 specific things. The old version of the test
which checks for read values is now covered by the generic test in
the sensor build_all target.
Signed-off-by: Yuval Peress <peress@google.com>
Add support for getting the following attribute values:
- SENSOR_ATTR_OFFSET
- SENSOR_ATTR_SAMPLING_FREQUENCY
- SENSOR_ATTR_FULL_SCALE
Signed-off-by: Yuval Peress <peress@google.com>
The logic in the driver was not aligned to the datasheet. Also,
temperature reading was not being done in fetch, but in channel_get.
There was also some extra conversions from SI->register->SI when
setting the range, this was causing the register value calculation to
produce an incorrect scale in some cases.
Tests were added to cover these cases.
Signed-off-by: Yuval Peress <peress@google.com>
Update the backend for sensor emulators to include a function for
setting the offset as well as a function to query an attribute's
metadata such as bounds and increment size. Additionally, add
backend support for setting the _xyz channel values.
Make the appropriate test changes to accomodate.
Signed-off-by: Yuval Peress <peress@google.com>
Ignore communication faults of the TLE9104 which are reported
before the communication watchdog is configured.
Fixes#67370
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Reduce some of the arithmetic required to decode a sample. Math is
documented in bma4xx_convert_raw_accel_to_q31.
This improved the accuracy from roughly 0.865mm/s2 to 0.001mm/s2 when
stationary and using a range of 4g.
Signed-off-by: Yuval Peress <peress@google.com>
ssize is a POSIX.1-2001 extension, which may or may
not be provided by the C library, or may be defined
to a different size in the host and embedded C library.
Two internal functions were returning ssize.
As these functions were just trampolines
into the same host API, which are already provided
by the native simulator let's just use those.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
ssize is a POSIX.1-2001 extension, which may or may
not be provided by the C library, or may be defined
to a different size in the host and embedded C library.
Two internal functions were returning ssize, but
one of them was a trampoline into the same host API,
which is already provided by the native simulator
so let's just use that instead.
The other is only carrying data that fits into an
int and is anyhow being cast in/to ints, so let's just
avoid the trouble by defining it as returning int.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The current driver initializes the IADC with the default configuration
(IADC_INITSINGLE_DEFAULT), which aligns the data to the right.
To correctly read the 12-bit sample, it should be masked from the right
instead.
Signed-off-by: Paulo Santos <pauloroberto.santos@edge.ufal.br>
Calling I2S write with less bytes than I2S TX memory block size makes it
possible to synchronize the time when next block is used against some
other, possibly externally sourced, signal. Example use case includes
USB Audio where audio sink and/or source has to be synchronized against
USB SOF. In Asynchronous synchronization type the rate matching is
achieved by varying the number of samples sent/received by 1 sample
(e.g. for 48 kHz audio, 47 or 49 samples are transmitted during frame
instead of 48).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Fix the log level of two LOG_ERR() statements which should have always
been LOG_INF(). As confirmed by the author Adrian in #60172
Fixes commit 3fbaed4de9 ("dai: intel: ace: dmic: Refactor of
dai_nhlt_dmic_dai_params_get function")
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Employ a code spell checking tool to scan and correct spelling errors
in all files within the drivers/i2c directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
.bss and .data are uncached in Zephyr builds for intel_adsp. No need
to try to manipulate cache of objects in those sections.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Driver is using the RISC-V PLIC interrupt controller without including
the necessary headers.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Employ a code spell checking tool to scan and correct spelling errors
in all files within the drivers/serial directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Employ a code spell checking tool to scan and correct spelling errors
in all files within the drivers/spi directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Employ a code spell checking tool to scan and correct spelling errors
in all files within the drivers/gpio directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
According to hardware spec, host dma needs some delay to completely stop.
In the bug the host dma is disabled in different path in a few microseonds.
The first setting disabled the host dma and called pm_device_runtime_put
to power off it. The second setting found the host dma was still alive
and calle pm_device_runtime_put again. This results to pm->usage
checking failed.
BugLink: https://github.com/thesofproject/sof/issues/8686
Signed-off-by: Rander Wang <rander.wang@intel.com>
Add support for the 1KHz counter. Update the RTC
driver to allow the 1Hz and high resolution counters
to exist together.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
In order to avoid build failures as described in issue #67242,
make all ST drivers using HAL_ST module dependent to HAL_STMEMSC
and HAS_STLIB libs, which need to be configured in all samples
referring to them.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This is a driver targetting the Bosch BMA 4-series accelerometers. It
has been specifically developed for the BMA422 but should be compatible
with others in that line, excepting the BMA400. Supports key attributes
and async RTIO one-shot operation. I2C operation is supported, with
stubs for a SPI implementation provided for future improvement.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
When using one of the internal channels (die_temp, vbat, vref) the
channels are enabled in the individual drivers and disabled again
whenever an adc conversion is complete.
This creates a race condition if the ADC is used from multiple threads.
This commit moves the disabling of the channels to the individual
drivers.
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
ERRATA 051421 states that if the SAI is FSYNC/BCLK master,
one of the directions is SYNC with the other, and the
ASYNC direction has the BYP bit toggled, the SYNC direction's
BCLK won't be generated properly.
This commit fixes this issue by enabling BCI for the SYNC
direction. What this does is it makes the SYNC direction use
the BCLK from the ASYNC direction's pad, which, if the BYP
bit is toggled, will be the undivided MCLK. Without this fix,
the SYNC direction will use the ASYNC direction's BCLK obtained
by dividing the MCLK via the following formula: MCLK / ((DIV + 1) * 2).
This is wrong because the ASYNC direction will use an undivided
MCLK while the SYNC direction will use a divided MCLK.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
With the introduction of the "rx_sync_mode" and "tx_sync_mode"
properties, the user may choose which synchronization mode the
SAI should use. To support this, the code had to be changed a
bit such that the software reset and the disable operations
work on all synchronization modes.
What this commit does, is it changes the software reset and
disable sequences such that they work with any of the
supported synchronization modes. Also, the syncMode field
of sai_transceiver_t structure is set to the value passed
from the DTS during sai_config_set().
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
In preparation for supporting all synchronization modes, this
commit introduces the rx_sync_mode/tx_sync_mode DTS properties.
Using these, the user will be able to specify which synchronization
mode the SAI should use.
At the moment, the driver does nothing with the values from
said properties but still checks if their values are sane
(i.e: it checks if the directions are both in SYNC mode which
is forbidden). By default, if "rx_sync_mode" or "tx_sync_mode"
is not specified, the direction will be set to ASYNC mode.
As such, below one may find a couple of valid examples
depicting this idea:
tx_sync_mode = <0>;
rx_sync_mode = <0>;
is the same as not specifying any of the properties,
tx_sync_mode = <1>;
rx_sync_mode = <0>;
is the same as:
tx_sync_mode = <1>;
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.
Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
ESP32 - S2,S3 and C3 variants have only 14 bits counter.
where as the plain ESP32 variant has 20 bits counter.
application failed to set low frequency(1Hz) in S2, S3 and C3 variants.
to get very low frequencies on these variants,
frequency needs to be tuned with 18 bits clock divider.
so select the slow clock source (1MHz) with highest counter resolution.
this can be handled on the func'pwm_led_esp32_timer_set' with 'prescaler'.
Signed-off-by: Jeeva Kandasamy <jkandasa@gmail.com>
Some MCU have limitations with GPIO interrupts. Add a polling mode to
the gpio-keys driver to support those cases.
This required a bit of a refactoring of the driver data structure to add
a instance wide data, and move the pin specific pointer in the config
structure.
For polling, reuse the button 0 delayed work so we minimize the resource
waste, the two work handler functions are only referenced when used so
at least those are discarded automatically if no instance needs them.
Fix a bug in the PM structure instantiation as well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Adjusted the code to guarantee resource release irrespective of operation
success or failure.
Fixes#67336
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
__bswap_ in zephyr/sys/byteorder.h conflicts with __bswap_ in host's
byteswap.h. byteswap.h from host compiler used in posix_native_64 boards
causes a compilation issue.
This commit renames __bswap_ to BSWAP_ to prevent collision.
Before this commit a compilation error can be created by adding #include
<byteswap.h> to samples/net/sockets/echo/src/socket_echo.c
This does not change external API to byteorder.h, but does change
internal implementation which some other source files depend on.
Replaced manual byteswap operations in devmem_service.c with APIs from
byteorder.h which automatically converts to CPU endianess when necessary.
Fixes#44324
Signed-off-by: Jonathan Hamberg <jonathanhamberg@gmail.com>
With commit 1d7476af, it fixed a build error with config
structure no longer having a base address field but left
the local variable defined. This resulted in a build warning
of an unused variable 'config' in two places.
Signed-off-by: David Leach <david.leach@nxp.com>
