Add a custom driver that takes care of loading and launching RISC-V VPR
cores found on the new nRF54 SoCs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
... in the related parts, so that the driver can be used on nRF54H20
where the clock control is not present yet.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On nRF54H20, only the new shim can be used and the enhanced poll out
cannot be enabled since there is no DPPI support for this SoC yet.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Move code that prepares `NRFX_CONFIG_GRTC_*` definitions based on
information from devicetree from the nRF54L15 nrfx_config header
to the global one, so that the code can be used by nRF54H20, too.
The checks that validate owned-channels and child-owned-channels
DT properties are moved to the nrf_grtc_timer driver so that
the global nrfx_config is not polluted unnecessarily.
The default values in nrfx_config_nrf54l15_enga_application.h
are restored to those from the corresponding template file.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds new NXP mailbox driver for MBOX device.
NXP mailbox IP driver supports sending data between cores.
It uses 32 bit register to trigger irq to other core.
This driver implementation uses 4 bits for channel selection of
triggering mode, 4 bits for channel selection of data transfer and
rest 24 bits for data.
NXP mailbox IP Reference Manual UM11126, Chapter 52.
https://www.nxp.com/webapp/Download?colCode=UM11126
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Address and size are given by the DTS register property
of the qspi nor : to be used by the qspi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor : to be used by the ospi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add power management support to the gpio-qdec driver.
This is a bit complicated by the fact that the driver has two modes of
operation and the interrupt, timer and idle work ineract with each
other.
The suspend sequence is:
- set the suspended bit (inhibits the poll timer so that it does not
resubmit the idle work)
- cancel the idle work (so that it does not schedule and re-set the
interrupt or timers)
- disable interrupts (if used)
- stop the sampling timer
- disconnect the pins
The resume sequence is more or less the opposite.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Some devices like S32K1xx don't feature an internal 32.768 KHz
oscillator. Also, updated the code to use the existing HAL API
for this purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
These changes enable -
1. S32 gmac driver to gracefully handle
net iface down and up net shell commands and
2. Link connect or disconnect events between
Ethernet PHY and its link partner.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Currently, whenever performing TRIGGER_PAUSE operation, the
data line is not disabled. This works well if TX and RX don't
operate at the same time or they operate in ASYNC-ASYNC mode. This
is because sai_tx_rx_disable() will disable transmitter/receiver
all the time since there's no dependencies to take into consideration.
However, in the ASYNC-SYNC mode, sai_tx_rx_disable() may not disable
the current asynchronous side if the synchronous side is still enabled.
As a consequence, the asynchronous side will remain enabled, thus
leading to an underrun/overrun.
To fix this issue, sai_trigger_pause() should disable the data line
each time it's called. This way, even if sai_tx_rx_disable() doesn't
disable the current direction, the data line will be disabled, thus
stopping the consumption/production of frames.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Supurious interrupts can be generated when the SPI device
is disabled. Ignore them within the SPI IRQ handler.
Co-authored-by: Georgij Cernysiov <geo.cgv@gmail.com>
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Allow to use H7 SPI FIFO to improve performance.
SPI FIFO usage can be enabled/disabled from devicetree.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Set the transfer size in SPI H7 and check EOT instead of TXC
to be sure the transaction has finished. This is required to
enable the use of the SPI FIFO, as otherwise SPI seems to
operate in "continuous mode", which produces several SCK cycles
after the last frame has been sent/received. More details in the PR.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
In many cases suspending or resuming of a device is limited to
just a few register writes. Current solution assumes that those
operations may be blocking, asynchronous and take a lot of time.
Due to this assumption runtime PM API cannot be effectively used
from the interrupt context. Zephyr has few driver APIs which
can be used from an interrupt context and now use of runtime PM
is limited in those cases.
Patch introduces a new type of PM device - synchronous PM. If
device is specified as capable of synchronous PM operations then
device runtime getting and putting is executed in the critical
section. In that case, runtime API can be used from an interrupt
context. Additionally, this approach reduces RAM needed for
PM device (104 -> 20 bytes of RAM on ARM Cortex-M).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add cleanups to pin presence checks within the mipi_dbi SPI driver.
The cleanups now verify that GPIO and RESET pin devices are ready,
if they are present for the device instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use a delegate for reporting the core clock rate of the fake CAN
driver. This allows overriding the delegate at run-time and inspecting its
call count.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Promote clk_ratio_adj to double for internal calculations related to ratio
to avoid compilation warnings related to implicit conversion from float
to double.
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
This adds support for the GRLIB SPIMCTRL SPI controller used in LEON and
NOEL-V systems. SPIMCTRL can operate in two different modes: In the
default mode it allows memory-mapped read access to the flash data. When
set in the user mode, it can be used to generate SPI bus transactions.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Support SFDP probe in flexspi nor driver. This probe will allow the
flash driver to dynamically configure quad spi flashes for 1-4-4 mode,
expanding the flash chips supported with this driver.
The following data is read from the SFDP header:
- quad enable method
- fast read command (1-4-4 is maximum supported)
Fixes#55379
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking flexspi in ccm_rev2 driver. Clock update
functions are provided for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the shared IRQ handler function in the shared interrupt controller
drivers to include support for the 'irq_number' parameter. When a single
driver manages multiple shared IRQs, it becomes challenging to determine
which IRQ line is invoking the handler. Therefore, I've introduced an
option to share the IRQ number to address this issue.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
eb2e5de01c made this a console driver but without adding the needed
hooks. This adds the hooks to support the console interface.
Fixes#65987Fixes#66264
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add the white light channel to the
veml7700 sensor to allow for correction
of light sources with strong infrared
content.
Signed-off-by: Jeff Welder <Jeff.Welder@ellenbytech.com>
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI controllers can easily implement MIPI DBI mode C, with the help of
GPIO pins for the reset and command/data signals. Introduce a MIPI DBI
compliant SPI driver, which emulates MIPI DBI mode C (SPI 3 and 4 wire).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce MIPI DBI driver class. MIPI DBI devices encompass several
interface types. All interfaces have a data/command, reset, chip select,
and tearing effect signal
Beyond this, MIPI DBI operates in 3 modes:
Mode A- 16/8 data pins, one clock pin, one read/write pin. Similar to
Motorola type 6800 bus
Mode B- 16/8 data pins, one read/write pin. Similar to Intel 8080 bus
Mode C- 1 data output pin, 1 data input pin, one clock pin.
Implementable using SPI peripheral, or MIPI-DBI specific controller.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The LIS2DE12 is an ultra-low-power high- performance three-axis
linear accelerometer belonging to the “femto” family with digital
I2C/SPI serial interface standard output.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lis2de12.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add APIs to:
1. read/write sensor regs on i2c/spi bus enabling adrress
auto-increment in a stmemsc specific way.
2. read/write sensor custom APIs.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
1. Support the dma mode for andes_atcspi200
and use board adp_xc7k_ae350 for testing.
2. Refine the function mechanism.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
1. Remove the redundant code.
2. Use sys_set_bits and sys_clear_bits instead of customized MACRO.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
Add driver for the Microchip Polarfire SOC MSS SPI controller.
The interrupts of the MSS SPI are routed through PLIC(Platform level
interrupt controller).
Tested with generic spi-nor flash driver(spi_flash) with both Fixed
flash configuration and Read flash parameters at runtime(using SFDP).
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
