At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.
Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Fixes compile warning:
drivers/eeprom/eeprom_emulator.c:645:13:
warning: 'rc' may be used uninitialized [-Wmaybe-uninitialized]
645 | int rc;
Signed-off-by: Nick Ward <nix.ward@gmail.com>
Fix settings for TEAR and DPHYCMD0 to match initialization data
provided by MCUX SDK driver. The following fixes were needed:
- Tear effect signal should only be sent at the VBLANK interval, so TEON
should be set to 0x0
- DPHYCMD0 LP-RX VHYS trimming was incorrectly being set to 37mV, when
it should be set to 66mV (the default value)
These changes resolve some flickering and blooming that occasionally
occurred during initialization
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit names a couple of choices to allow the default
value to be overridden by Kconfig files out of tree
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
Since the accelerometer's HM (high-performance mode) bit is forced to 1,
the 1.6Hz frequency is available by setting the ODR to 11.
1.6Hz is a low-power mode that conserves energy and is suitable for
some applications, such as determining the orientation (portrait or
landscape) of a device.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Build errors where introduced by
c76d5b882c and are fixed with this
commit. They are trivial fixes of malformed lines.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Add in DT the possibility to configure both INT1 and INT2
pin. The driver will then assign one of the two (either 1
or 2, according to what value drdy_pin is set) to a gpio
for receiving drdy interrupts.
The other pin may be used in the future to receive event
interrupts.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The HCI receive path has a delay between reading the header and payload
from the controller to give the controller time to setup the SPI
peripheral for the next transaction. Add the same delay on the transmit
path for the same reasons.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add log output when the HCI interface is forced to retransmit a packet
because the controller is not ready.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The way that the QSPI peripheral is activated has been changed in
nrfx 3.2.0. Now the peripheral is not activated during the driver
initialization. Instead, the driver activates the peripheral when
the first operation is requested or when `nrfx_qspi_activate()` is
called. In case of XIP, the latter needs to be used, as there may
be no standard operation request.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.
Update NXP HAL to remove this Kconfig as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The init scripts need a missing wait for OK after sending
AT+CGMM and the AT+CMUX command specifies more parameters
than nessesary, and in some cases incorrectly.
This commit adds the missing wait for OK and fixes the AT+CMUX
commands in the init scripts.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
1. Issue a reset during init to ensure the registers
are in their reset state.
2. The value in counter_set_top_value was not written
to the register. This function now returns -ENOTSUP
3. Make sure the RTC is enabled before we issue RTC_Start
command.
4. Replace calls to SDK API's RTC_StartTimer and
RTC_StopTimer with RTC_EnableTimer
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This chip uses an active low reset, so the correct behavior here is to
define the pin as ACTIVE_LOW, using GPIO_OUTPUT_ACTIVE to assert the
reset and set to 0 to deassert.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This chip uses an active low reset, so the correct behavior here is to
define the pin as ACTIVE_LOW, using GPIO_OUTPUT_ACTIVE to assert the
reset and set to 0 to deassert.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The current code deasserts the reset, just to re-assert it immediately.
Just initialize with OUTPUT_ACTIVE, delay and then de-assert.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix the SFDP command to be sent by the qspi driver
to get the SFDP table from the NOR quad flash.
Note that CONFIG_FLASH_STM32_QSPI=y and CONFIG_SPI_NOR=n
HAL_DMA_Abort declared as weak to fix compilation error with stm32f7x
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move the syscall_handler.h header, used internally only to a dedicated
internal folder that should not be used outside of Zephyr.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Modify SPI configuration to match the features introduced in PR #63437.
Set the property "controller-data-delay-us" to zero for boards
which are using BlueNRG-MS.
Fix Chip Select configuration for stm32l562e_dk board.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Real UARTs usually write 1 to a few bytes at a time through a
latch buffer. Add latch buffer property to binding for
uart_emul and limit fifo_read and fifo_fill to not exceed the
latch buffer.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Define local thread to emulate different thread priorities.
A UART driver may call back from within a thread with higher
or lower priority than the thread calling the UART API. This
can hide potential concurrency issues, especially if the
thread priorities are the same, or even using the same thread
in case the system work queue.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
