Extend the lan9250 driver to support using a local administered
unicast random mac address during init. This follows the device tree
settings for zephyr_random_mac_address from other ethernet drivers
for the added support.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
The SCMI CPU protocol is in fact a vendor extension from NXP. The current
naming used for the CPU protocol definitions (i.e. functions, structures,
macros) follows that of the SCMI standard protocols, which might be
misleading.
Include "nxp" in the name of all of the CPU protocol definitions.
This change was performed mechanically using "git grep" and "sed -i"
with some manual intervention.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
When the firmware wrote data to KBC/AUX output buffer, the hardware
automatically generated IRQ1/12 to notify the host. After the host read
the data, the EC received an output buffer empty (OBE) interrupt to
indicate that the next byte could be written. However, on the NPCX9M7FB,
this mechanism may cause IRQ1/12 to be missed if the firmware write new
data immediately after detecting that the output buffer is empty,
resulting in incorrect behavior.
To avoid missing IRQ1/12, the flow is changed so that it first checks
VWIRE_AVAIL to ensure no pending VW events. If no VW event is pending,
the firmware writes data to the output buffer and explicitly asserts
IRQ1/12 to notify the host. After the host reads the data and the OBE
interrupt triggers, the firmware clears IRQ1/12.
This updated sequence prevents IRQ1/12 from being lost and ensure
correct notification behavior.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
The device_map() is not defined for SoCs with no MMU, add the
device_map() macro when !DEVICE_MMIO_IS_IN_RAM to support building for
SoCs with no MMU.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Allow passing some context to the shell bypass callback function by
providing a void pointer user data argument.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Improve the logic for detecting counter wrap-around events when exiting
low power mode.
Add idle_timer_alarm_ticks variable to track alarm configuration at LPM
entry. Implement comprehensive wrap detection that considers:
- Counter overflow (pre > post)
- Alarm pending with same pre/post values
- Alarm pending when pre + alarm_ticks would exceed counter top value
This ensures accurate time calculation across all counter wrap scenarios
during low power mode transitions.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
- Add new hardware info driver for Microchip G1 series.
- Update Kconfig and CMakeLists.txt to support the new driver.
Signed-off-by: Farsin Nasar V A <farsin.nasarva@microchip.com>
Incorrect symbols were used for detecting nRF5340 Network-specific
reset reasons presence.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
If spi_sam_configure() is called with more than 4 chip selects the
current check fails even if the pins are used as gpios. The variable
spi_csr_idx already has the correct index to be checked and must be
used in this check.
Signed-off-by: Munawar Ali <ali@sofiha.de>
Signed-off-by: Axel Utech <utech@sofiha.de>
If the event timer or free-run timer is close to expiration when
system enters idle with I2C target DMA mode enabled, the memory
and CPU clocks may become unsynchronized after wakeup. This
causes CPU to fetch incorrect data and eventually trigger SoC
watchdog timeout.
Due to this hardware limitation, SoC should skip entering idle
mode if the remaining timer value is less than 150µs(safe margin).
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Returning `-ENOTSUP` (and logging a `LOG_ERR`) is not the correct
behaviour if there is no enable GPIO. The fact there was no work to do
does not make the result an error.
From the docs for `pm_device_runtime_get`
```
* @retval 0 If it succeeds. In case device runtime PM is not enabled or
* not available this function will be a no-op and will also return 0.
```
Signed-off-by: Jordan Yates <jordan@embeint.com>
Minimal changes to OV760 drive to use generic ov767x structures.
- This includes changes to function names.
- Includes changes to defines as necessary.
- Deleted camera_id as no longer required
Signed-off-by: Michael Smorto <CyberMerln@gmail.com>
This commit introduces a new comparison for the ARM (AArch32) architecture
in the GICv3 interrupt controller.
It specifically compares the lower 24 bits of the affinity values,
because there is no aff3 in AArch32 or Arm-v7.
Signed-off-by: Guowei Li <15035660024@163.com>
Allows "egis_et171_spi" to use basic clock information
provided by the clock driver to calculate the runtime
SPI frequency.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
The Cadence SPI controller has a hardware issue (Xilinx AR#65885
contains more details) where the RX_NOT_EMPTY (RNE) status bit
reports inconsistent state. This causes the driver to unreliably
detect when RX FIFO contains valid data, leading to transfer
failures and test hangs.
Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Microchip MEC parts have a similar GPIO peripheral block. We
create a unified driver for all parts. NOTE: MEC GPIO interrupt
detection sets active status when changed from interrupt detect
disabled to any enabled mode. Driver ISR and interrupt configuration
implementation includes work-arounds for this issue.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Setting a prescaler of 256 would overflow the uint8_t.
Also get cycles calculation was wrong.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
add driver and dts-binding for kinetis_scg driver
used on ke1xz
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Signed-off-by: Michael Galda <michael.galda@nxp.com>
In install timeout api, the cfg parameter does not make sense to cop, we
can ignore it rather than return an error code to keep forward
compatibility.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
The mcux_adc16 driver's read function fails to validate the user-provided
buffer size when `adc_sequence.options` are used (extra samplings).
The calculation erroneously considered only the size required for one
channel, neglecting the total number of channels in the sequence.
This leads to a **buffer overflow** when reading multiple channels.
Fix this by using `POPCOUNT(sequence->channels)` to determine the
correct channel count and ensure the buffer size is sufficient.
Signed-off-by: Badr Bacem KAABIA <badrbacemkaabia@gmail.com>
1. Fix wrong backlight pin in driver overlay
2. Remove the power-on pin configuration in code and binding, and
add mipi display panel regulator in panel overlay instead. Set
regulator-boot-on' to true means the power-on pin will be enabled
uring system boot.
3. Remove 'last_known_framebuffer' from panel data structure. It is
not used anywhere
4. Fix bug in 'co5300_set_pixel_format' function.
5. Fix the issue that the panel does not support start coordinates
and the width/height of the updated area being odd value.
Solution: In panel driver, maintain a full screen-sized buffer,
its address and pitch alignment is configurable in device tree
and shall be compliant with the display controller's requirements.
It can be placed in RAM or if the RAM space is not enough it can
also be placed in other memory resion. When there is a frame
update request, the updated area will be first filled to the
buffer, if the area's size or coordinate is odd, adjust the value
so the real updated area covers the requested updated area, then
use this buffer to send pixel to panel, this can ensure the
updated area's size and coordinate are always even.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
The irq_lock area including net_pkt_rx_alloc_with_buffer() was causing
error "Context switching while holding lock!".
Actually we didn't have any hardware access to protect in netc_eth_rx,
so just removed irq_lock.
Fixes#99694
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
For stm32h7 the order matters to get the pwm to output the values as
expected. As reported for the the H730 doesn't produce PWM output when
the LL_TIM_OC_SetDeadTime is called after LL_TIM_EnableAllOutputs. So,
switch the order of the calls and this doesn't impact the stm32f413zh
boards.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Extend the number of SPI data sizes supported for series that allow it.
The driver uses the new property st,stm32-data-width to create a table
with all compatible data widths and to check if the SPI instance
support the required width (some instances may have a limited set
of widths compared to others on the same SoC).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Inverts ll_func_spi_dma_busy logic so that the function returns true if
the SPI DMA is busy (as suggested by the name) instead of the other way
around.
Also completes the check for H7-compatible with the LL_SPI_IsActiveFlag_EOT
function when transfer size is set.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The xmc47_relax_kit i2c driver is incorrectly using the
I2C_SPEED_STANDARD macro to set the clock frequency. The correct macro
to use is XMC4_I2C_SPEED_STANDARD which is defined by the XMC4 driver.
Signed-off-by: Yassine Safraoui <yassine.safraoui@grenoble-inp.org>
Guard callback registration with CONFIG_SPI_ASYNC to avoid
build error for blocking SPI transfers using DMA
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Swap the write and read data paths within the GSPI controller to ensure
correct data is seen on the SPI lines during 16-bit transfers.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Updated mosi_overrun alignment from 4 bytes to 32 bytes to
ensure compatibility with the GPDMA driver. This prevents
alignment-related errors during DMA transfers.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Enable higher SPI burst sizes when using GPDMA to improve throughput.
Bursts are only enabled when both TX and RX channels use GPDMA and
the SPI clock frequency is at least 10 MHz, as DMA flow control is
unreliable at lower SPI rates.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Add gspi_siwx91x_pick_lower_freq() to select the nearest lower
supported GSPI clock frequency based on the requested value.
The GSPI clock can operate only at discrete frequencies such as
80 MHz, 40 MHz, 26.6 MHz, 20 MHz, and so on (80 MHz divided by
integer factors). If the requested frequency does not match one
of these valid steps, it is rounded down to the nearest lower
supported frequency.
The driver now logs both the requested and the actual programmed
frequency along with the divider value, helping users verify the
effective SPI clock configuration.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
The GSPI and QSPI peripherals run on the interface PLL clock.
To ensure correct operation, the interface PLL frequency should
be set to 160 MHz. This provides a base clock of 80 MHz to the
QSPI peripheral, which matches its required operating frequency.
The GSPI peripheral can continue to operate at higher frequencies
as it receives the full interface PLL clock.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
The existing device runtime PM model requires applications to call
pm_device_runtime_get()/put() on the GPIO controller device directly,
which is not ideal when GPIO ports are exposed as child nodes.
This update enables runtime PM at the GPIO port (child node) level,
allowing applications to manage power through the port devices instead
of the top-level controller.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Add `get_calibration` and `set_calibration` subcommands to allow users
to read and modify the RTC calibration settings from the shell.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
