When using one of the internal channels (die_temp, vbat, vref) the
channels are enabled in the individual drivers and disabled again
whenever an adc conversion is complete.
This creates a race condition if the ADC is used from multiple threads.
This commit moves the disabling of the channels to the individual
drivers.
Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
ERRATA 051421 states that if the SAI is FSYNC/BCLK master,
one of the directions is SYNC with the other, and the
ASYNC direction has the BYP bit toggled, the SYNC direction's
BCLK won't be generated properly.
This commit fixes this issue by enabling BCI for the SYNC
direction. What this does is it makes the SYNC direction use
the BCLK from the ASYNC direction's pad, which, if the BYP
bit is toggled, will be the undivided MCLK. Without this fix,
the SYNC direction will use the ASYNC direction's BCLK obtained
by dividing the MCLK via the following formula: MCLK / ((DIV + 1) * 2).
This is wrong because the ASYNC direction will use an undivided
MCLK while the SYNC direction will use a divided MCLK.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
With the introduction of the "rx_sync_mode" and "tx_sync_mode"
properties, the user may choose which synchronization mode the
SAI should use. To support this, the code had to be changed a
bit such that the software reset and the disable operations
work on all synchronization modes.
What this commit does, is it changes the software reset and
disable sequences such that they work with any of the
supported synchronization modes. Also, the syncMode field
of sai_transceiver_t structure is set to the value passed
from the DTS during sai_config_set().
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
In preparation for supporting all synchronization modes, this
commit introduces the rx_sync_mode/tx_sync_mode DTS properties.
Using these, the user will be able to specify which synchronization
mode the SAI should use.
At the moment, the driver does nothing with the values from
said properties but still checks if their values are sane
(i.e: it checks if the directions are both in SYNC mode which
is forbidden). By default, if "rx_sync_mode" or "tx_sync_mode"
is not specified, the direction will be set to ASYNC mode.
As such, below one may find a couple of valid examples
depicting this idea:
tx_sync_mode = <0>;
rx_sync_mode = <0>;
is the same as not specifying any of the properties,
tx_sync_mode = <1>;
rx_sync_mode = <0>;
is the same as:
tx_sync_mode = <1>;
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.
Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
ESP32 - S2,S3 and C3 variants have only 14 bits counter.
where as the plain ESP32 variant has 20 bits counter.
application failed to set low frequency(1Hz) in S2, S3 and C3 variants.
to get very low frequencies on these variants,
frequency needs to be tuned with 18 bits clock divider.
so select the slow clock source (1MHz) with highest counter resolution.
this can be handled on the func'pwm_led_esp32_timer_set' with 'prescaler'.
Signed-off-by: Jeeva Kandasamy <jkandasa@gmail.com>
Some MCU have limitations with GPIO interrupts. Add a polling mode to
the gpio-keys driver to support those cases.
This required a bit of a refactoring of the driver data structure to add
a instance wide data, and move the pin specific pointer in the config
structure.
For polling, reuse the button 0 delayed work so we minimize the resource
waste, the two work handler functions are only referenced when used so
at least those are discarded automatically if no instance needs them.
Fix a bug in the PM structure instantiation as well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Adjusted the code to guarantee resource release irrespective of operation
success or failure.
Fixes#67336
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
__bswap_ in zephyr/sys/byteorder.h conflicts with __bswap_ in host's
byteswap.h. byteswap.h from host compiler used in posix_native_64 boards
causes a compilation issue.
This commit renames __bswap_ to BSWAP_ to prevent collision.
Before this commit a compilation error can be created by adding #include
<byteswap.h> to samples/net/sockets/echo/src/socket_echo.c
This does not change external API to byteorder.h, but does change
internal implementation which some other source files depend on.
Replaced manual byteswap operations in devmem_service.c with APIs from
byteorder.h which automatically converts to CPU endianess when necessary.
Fixes#44324
Signed-off-by: Jonathan Hamberg <jonathanhamberg@gmail.com>
With commit 1d7476af, it fixed a build error with config
structure no longer having a base address field but left
the local variable defined. This resulted in a build warning
of an unused variable 'config' in two places.
Signed-off-by: David Leach <david.leach@nxp.com>
When usb middleware sends a start of frame notification to this driver,
call status_cb with USB_DC_SOF.
Signed-off-by: James Zipperer <jzipperer@fb.com>
Add an input driver to read data from an analog device, such as a
thumbstick, connected to an ADC channel, and report it as an input
device.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add driver that based on RPI-PICO's PIO feature for ws2812.
This driver can handle WS2812 or compatible LED strips.
The single PIO node can handle up to 4 strips.
Any pins that can be configured for PIO can be used for strips.
I verified the samples/driver/led_ws2812 sample
working with WS2812(144 pcs) led strip using following patches.
- samples/drivers/led_ws2812/boards/rpi_pico.overlay
```
/ {
aliases {
led-strip = &ws2812;
};
};
&pinctrl {
ws2812_pio0_default: ws2812_pio0_default {
ws2812 {
pinmux = <PIO0_P21>;
};
};
};
&pio0 {
status = "okay";
pio-ws2812 {
compatible = "worldsemi,ws2812-rpi_pico-pio";
status = "okay";
pinctrl-0 = <&ws2812_pio0_default>;
pinctrl-names = "default";
bit-waveform = <3>, <3>, <4>;
ws2812: ws2812 {
status = "okay";
output-pin = <21>;
chain-length = <144>;
color-mapping = <LED_COLOR_ID_GREEN
LED_COLOR_ID_RED
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
};
};
};
```
- samples/drivers/led_ws2812/boards/rpi_pico.conf
```
CONFIG_WS2812_STRIP_RPI_PICO_PIO=y
```
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Use proper register mask for software reset register so
reset magic value sent to device is not malformed.
Co-authored-by: Bartosz Bilas <b.bilas@grinn-global.com>
Signed-off-by: Lukasz Madej <l.madej@grinn-global.com>
While waiting for the UART to be ready in ISR
mode, for simulation only, add a tiny delay per
iteration of the busy wait loops to allow
time to pass.
This Z_SPIN_DELAY is an empty macro for any
other target than simulation.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Instead of getting the hardcoded address from the DT structure
use its symbolic name which will be resolved by the nRF HAL
definitions to the same value.
This allows the TIMER peripherals' addresses to be redefined
for the simulated targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The ISR prototype is not matching the
signature for interrupt handlers, which results in
build warnings.
Let's fix it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
For simulation, we cannot get the UART regiter address
for the pinctrl config structure from DT, as that
cannot match the one allocated at build time.
So let's override it at runtime with the correct address
which is stored in the UART config structure.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Instead of getting the hardcoded address from the DT structure
use its symbolic name which will be resolved by the nRF HAL
definitions to the same value.
This allows the GPIO peripherals' addresses to be redefined
for the simulated targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The ISR prototype used when building without the
interrupt driven UART was not matching the
signature for interrupt handlers, which results in
build warnings.
Let's fix it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Interrupt trigger type register each bit indicate the configured interrupt
type. bit value is 0 indicate level trigger interrupt, 1 indicate edge
trigger interrupt.
The level trigger defined to ~BIT(0) equal 0xfffffffe not equal 0.
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
A Zero Length Packet can be used by higher layer stack to discover when
an endpoint is being processed by the host. An example of this was
introduced as part of 0127d000a2 ("usb: device: cdc_acm: Use ZLP to
detect initial host read") in the CDC ACM class.
Not invoking the callback for ZLPs results in the higher layer stack not
being informed when the packet is consumed. This manifests as a CDC ACM
USB-IP device that cannot transmit to the host while being able to
receive from the host.
Signed-off-by: Abe Kohandel <abe.kohandel@gmail.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit partially reverts a change which was introduced in the
previous commit 5b9a0e5456.
usb_dc_ep_start_read() should also be called on transfer endpoints
like it has been before, otherwise the endpoint will not be armed
after it has been reconfigured.
Signed-off-by: Manuel Aebischer <manuel.aebischer@netmodule.com>
... so that it is possible to use a GPIO expander pin as the CS line.
Communication with the expander may involve an operation that cannot
be done from the interrupt context (e.g. an I2C transaction).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit ea1be7f242.
After the driver performs its initialization, it needs to deactivate
the QSPI peripheral. Otherwise, the peripheral would unnecessarily
consume power until some QSPI operation is performed (and only then
it will get deactivated), what depending on the application may take
a significant amount of time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
`release` is a mandatory method in the `struct spi_driver_api` API but
is not implemented in the SPI emulator. This can cause a test calling
`spi_release()` to segfault. Add a stub implementation that just returns
zero.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
With commit 734adf52c6, the MCUX LPI2C config structure no longer
contains a direct base address pointer. The base address must be
accessed via DEVICE_MMIO_NAMED_GET. Some declarations in the LPCI2C
target mode handler still used the old method of accessing the base
address, causing a build failure. Fix these accesses to use the local
declaration of the "base" variable.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
clangsa reports the error
mdio_nxp_enet.c:245:10: error: label at end of compound statement:
expected statement
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Added Kconfig assignment of qspi timeout.
Per nrfx v3.2 addition of qspi timeout in config
struct.
Signed-off-by: Kelly Helmut Lord <kellyhlord@gmail.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
