phy_tja11xx_get_link_state() always returns 0, making callers' error
checks ineffective.
Remove the unused return variable and drop the dead conditional in
invoke_link_cb() to silence static analysis warnings and simplify
the code.
No functional change.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Handle both multicast packets and promiscuous mode in the driver. This
will allow the lan9250 to be added to a bridge as well as process
multicast packets being received.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
The bus recovery implementation did not reset the I2C block. If
a glitch on the bus looks like a start condition, the I2C block
will be stuck forever waiting for the associated stop. This adds
reset to the I2C block to address this type of error.
Signed-off-by: Tim Knodel <tbk@google.com>
On STM32F446, F469, F479 and on STM32F7x, the CK48M mux can have either
PLL Q or PLLSAI P as input. Adds the support for the PLLSAI P input in
the driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move get_ck48_frequency function outside of the #if STM32_PLL_ENABLED
because it should be usable even if the main PLL is not used. The mux
can indeed be used with PLLI2S.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit updates the STM32Fx clock driver to add complete support for
all PLLs for all SoCs.
Supports all outputs and additional divisors:
- PLL-DIV-R
- PLLI2S-P
- PLLI2S-DIV-Q
- PLLI2S-DIV-R
Adds global checks to make sure that all:
- All PLLs share the same source clocks
- All PLLs share the same M-Divisor (on applicable SoCs)
- Both div-X and div-divX are defined (on applicable SoCs)
Functions get_plli2s_source and get_plli2ssrc_frequency are added to make
sure that PLLI2S can be used even if PLL is not defined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The Pico SDK expects a transfer count (items), not a byte count. The
driver incorrectly passed the byte size, causing buffer overflows on
16-bit and 32-bit transfers.Fix this by storing the transfer width in
the channel configuration and dividing the block size by that width
to calculate the correct transfer count.
Fixes#99435
Signed-off-by: Ashirwad Paswan <ashi06712@gmail.com>
Moving the reset of ltpim hw ip at the beginning of
sys_clock_driver_init to improve the reliability of lptim hw
configuration sequence.
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Switch SDL buffers from SDL_PIXELFORMAT_ARGB8888 to
SDL_PIXELFORMAT_BGRA32. BGRA32 is platform endianness independent
description, defined as below:
Byte 0 Byte 1 Byte 2 Byte 3
7......0 15.....8 23....16 31....24
Bbbbbbbb Gggggggg Rrrrrrrr Aaaaaaaa
The driver is then updated in order to ensure that all buffers,
given via a PIXEL_FORMAT_ described format are properly converted
into the SDL_PIXELFORMAT_BGRA32. At the same time endianness
conversion code is also added in order to avoid taking assumption
that the running platform is little-endian and ensure that data
are properly read as expected.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The format currently expected by devices and sample display
application for BGR_565 is actually RGB_565 format with bytes
swapped (not B / R swapped). That is:
PIXEL_FORMAT_RGB_565:
* @code{.unparsed}
* 7......0 15.....8
* | gggBbbbb RrrrrGgg | ...
* @endcode
current PIXEL_FORMAT_BGR_565:
* @code{.unparsed}
* 7......0 15.....8
* | RrrrrGgg gggBbbbb | ...
* @endcode
This is explained in both st7796s display driver but also is
what is generated by the sample display application. As a video
format (ex: V4L2), such format is not mentioned as BGR (for
which R and B are swapped) but RGB_565X.
Within the whole Zephyr tree, rename the curremt BGR_565 format
into RGB_565X in order to emphasis that this is a byte swapped
format rather than a B/G component swapped format.
This also correct the description of the format in display.h
file, which wasn't correct based on what was being used by
display driver or sample display app.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Fix formatting of the __ASSERT message in
mcux_ctimer_pwm_get_cycles_per_sec to properly concatenate the
string across multiple lines.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
entropy_gd32_recover() had not return type defined causing the
following issue when building:
drivers/entropy/entropy_gd32.c:61:8: error: return type defaults to
'int' [-Werror=implicit-int]
Fix it and change the function to void since it was returning a
constant 0 that is never checked or used.
Signed-off-by: Flavio Ceolin <flavio@hubblenetwork.com>
remove redunant tx mutex, as the networking
subsystem already provides one since
f65ac5effb02bdc4cb70b205545971e70c53c282
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Read the idle timer counter value after getting interrupt status and
top value to ensure more accurate timing measurements when exiting
low-power mode.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Clear pending SysTick interrupt before entering low-power mode when
CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM is enabled. A pending interrupt
can inhibit LPM entry or cause immediate wakeup. This is safe since
cycle_count was already updated.
Also improve RESET_BY_LPM Kconfig help text.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Move the descriptor storage into the per-instance data structure rather
than being global, as they should not be shared between instances.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The way the driver was storing IRQ numbers for later use in the various
locking modes was not correct, causing the wrong IRQs to potentially be
disabled/enabled in some modes. Refactor the way this is done to be
cleaner, and also the way the different locking modes are implemented in
order to ensure that all modes receive compile test coverage.
Also, ensure that the IRQ for the RX or TX channel is always disabled
during the execution of the corresponding ISR, to prevent it from being
preempted by itself if the DMA core raises another interrupt during the
ISR execution.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This driver has a config option
DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS to allow
it to be used on platforms where DMA memory access is not automatically
cache coherent. However, fully disabling the dcache when accessing DMA
buffers/descriptors is not necessary and is potentially problematic.
This can be handled more selectively by doing explicit cache invalidate
and/or flush operations on the buffers involved as required.
Note that this does introduce a requirement that RX DMA buffers provided
to the driver are cache line aligned, as otherwise the required cache
invalidate operation could potentially corrupt unrelated data. This is
explicitly checked when a DMA RX operation is started.
Tested on Cortex-R5 with data cache enabled.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The driver previously had a timer to periodically check for completed
TX/RX transfers in case an interrupt notification was missed. With
previous changes to the driver to avoid lost interrupt wakeups, this
workaround should no longer be required, so remove it.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Fix some issues in the driver's DMA interrupt handling:
-Ensure that interrupts are cleared prior to handling interrupt events,
so that events raised during interrupt processing will cause the
hardware to raise a new interrupt
-Ensure that we do not overwrite existing DMA descriptors which are
incomplete (such as by trying to execute more transfers than there are
slots in the descriptor ring)
-Ensure that error events reported by the DMA engine are reported
-Rename some of the variables to track pending and completed ring
locations for better clarity
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Doing a reset of the DMA engine during the dma_configure operation is
problematic when using the DMA core in combination with the Xilinx AXI
Ethernet core, since the DMA core's reset signals are normally
propagated into the Ethernet core. This means that after the Ethernet
core initializes and starts a DMA operation for the first time, the DMA
core is reset, wiping out all of the register settings that the Ethernet
core has made.
To avoid this, move the DMA core reset and other initialization which
only needs to be done once into the init function, so this is done
during initial driver load and not deferred until later.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Instead of using a packed structure to define the register map, just
create an enum for the registers and use that to refer to them. This
avoids the need for repeatedly disabling GCC warnings for taking the
address of packed structure members.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS
option is not meaningful to enable unless the platform/configuration
actually supports the corresponding cache maintenance operations. Add
dependencies accordingly.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
There's a standardized way to set a public Bluetooth address in the
core, and this hardware has a vendor specific command to do just that.
Tell the core we support the operation and implement the command. This
allows applications to set a MAC by calling bt_id_create() prior to
bt_enable().
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
If the vendor driver knows how to set a public MAC, it can select
CONFIG_BT_HCI_SET_PUBLIC_ADDR and set the address in this argument,
allowing applications to set a public address with bt_id_create().
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Implement interrupt settings to expand the driver to RZ/V2H, V2N SoCs
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
clock_control_bl60x_set_root_clock_dividers() never reports errors
and always returns 0.
The error check at the call site is therefore dead code.
Make the function void and drop the unused error handling.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
clock_control_bl70x_set_root_clock_dividers() never reports errors
and always returns 0.
The error check at the call site is therefore dead code.
Make the function void and drop the unused error handling.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
commit bf61a47887 ("drivers: sdhc: imx_usdhc: extend reset timeout
duration") extended the timeout from 100 iterations to 1000 iterations
for the USDHC_Reset() call in imx_usdhc_reset() but not in the other
places it's called. I have observed a "usdhc: Failed to reset command
line" error from imx_usdhc_error_recovery() on an i.MX RT1061, which
goes away if I extend the timeout. Do so there and also at other call
sites for good measure.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Factorize STM32 interface clocks configuration in a single array.
This change eases later integration of other SoCs with different
clocks names while the driver only has to enable (possibly disable)
the clocks on a single sequence.
Suggested-by: Fin Maaß <f.maass@vogl-electronic.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove helper macro used to transition from MAC clocks defined
by the MAC node to definition in the controller (parent) node.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Prepare move of STM23 ethernet MAC clocks to the controller node (parent
node). For sake of simplicity, define a filed for all possible clocks in
struct eth_stm32_hal_dev_cfg, a later change will replace the whole
with a single STM32 clock instance (struct stm32_pclken) array pointer.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Update STM32 ethernet driver to use STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macro to always get all clock information, not only the bus ID
and bit position.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add a new sleep-mode-enable property for the Cirque Pinnacle input driver,
to enable the sleep-mode for those peripherals, which will go into a lower
power state after 5 seconds with no fingers detected.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Don't rely on power-on-reset for the connected device, issue a software
reset on init to be sure we're reset before continuing.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
