Whenever UART_RX_DISABLED event is received module attempts to
re-enable receiver since in interrupt driven API receiver is
always on. However, it is possible that there is no free buffers
and in that case attempt to enable the receiver will fail with
-EBUSY. That scenario shall be accepted since the receiver will
be re-enabled when at least one buffer will be freed.
Given that, -EBUSY return shall be accepted (no assert) and
number of pending RX buffer requests shall be reset only on
successful enabling.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
return value of pwm_rpi_get_clkdiv contains implicit conversions
from 'float' to 'double', triggered by floating-point operations
involving mixed data types.
Signed-off-by: Jannis Ruellmann <j.ruellmann@kunbus.com>
Commit b2eaa6448076 ("drivers: dma: intel-adsp-hda: add delay to stop
host dma") added a wait on GBUSY state to host DMA stop.
This is problematic as in some case (like SOF chain-DMA usage),
the host DMA side RUN bit is not cleared when intel_adsp_hda_dma_stop()
is called. It is not possible to wait on GBUSY bit as there are
valid cases where it can remain set.
Address the original problem described in SOF bug #8686 and add a
polling check for intel_adsp_hda_is_enabled(). As per the bug
description, in some cases the GEN/FIFORDY bits are not cleared
immediately and if a new call to intel_adsp_hda_dma_stop() is made, the
PM refcounting will go haywire.
Link: https://github.com/thesofproject/sof/issues/8686
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The CST816S chip ID have an alternative value. It seems that this
field represents in fact a version number of controller. Fix by adding
the new chip ID.
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
Fix coverity integer handling issue (CWE-188).
Modifying a variable through a pointer of an incompatible type (other
than unsigned char) can lead to unpredictable results.
Fix: #67965
Coverity-CID: 248434
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Using the 8 base clock cycles per bit period setting (instead of 16)
reduces the uart baud rate error when using a 12MHz crystal (found on
many RA Microcontroller development kits boards). This setting also
slightly reduces the error when using the internal 48MHz oscillator,
used by the Arduino UNO R4 Minima board currently support by Zephyr.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
With the device_sync_sem semaphore, there is the possibility of
the code not returning to give it back
(mcux_flexcomm_master_transfer_callback is never called),
causing it to get stuck in k_sem_take(&data->device_sync_sem, K_FOREVER)
in subsequent calls.
The i2c driver recovers by other means
(enabling FSL_FEATURE_I2C_TIMEOUT_RECOVERY)
but the callback might not return.
Adding a timeout option allows for this occurrence to be avoided.
Signed-off-by: Guilherme Casa Nova <guilherme.casa_nova@dell.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Check the return code of mipi_dbi_reset, and do not delay for the reset
wait time unless the mipi controller has issued a hardware reset to the
display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix usage of MIPI buffer descriptor in ili9xxx driver. Previously, the
buffer descriptor size was being set to display buffer size. For cases
where the write height/width was not equal to the size of the buffer, this
resulted in additional data being written that was not needed. To
resolve this, calculate the mipi descriptor buffer size in the driver
Also, remove the unconditional setting of mipi_desc.height, as this
would override the previous (correct) setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a custom driver that takes care of loading and launching RISC-V VPR
cores found on the new nRF54 SoCs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
... in the related parts, so that the driver can be used on nRF54H20
where the clock control is not present yet.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Extend Kconfig definitions and nrfx_config translations so that UARTE
instances that are available in nRF54H20 can be used.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On nRF54H20, only the new shim can be used and the enhanced poll out
cannot be enabled since there is no DPPI support for this SoC yet.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Move code that prepares `NRFX_CONFIG_GRTC_*` definitions based on
information from devicetree from the nRF54L15 nrfx_config header
to the global one, so that the code can be used by nRF54H20, too.
The checks that validate owned-channels and child-owned-channels
DT properties are moved to the nrf_grtc_timer driver so that
the global nrfx_config is not polluted unnecessarily.
The default values in nrfx_config_nrf54l15_enga_application.h
are restored to those from the corresponding template file.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds new NXP mailbox driver for MBOX device.
NXP mailbox IP driver supports sending data between cores.
It uses 32 bit register to trigger irq to other core.
This driver implementation uses 4 bits for channel selection of
triggering mode, 4 bits for channel selection of data transfer and
rest 24 bits for data.
NXP mailbox IP Reference Manual UM11126, Chapter 52.
https://www.nxp.com/webapp/Download?colCode=UM11126
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Address and size are given by the DTS register property
of the qspi nor : to be used by the qspi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor : to be used by the ospi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add power management support to the gpio-qdec driver.
This is a bit complicated by the fact that the driver has two modes of
operation and the interrupt, timer and idle work ineract with each
other.
The suspend sequence is:
- set the suspended bit (inhibits the poll timer so that it does not
resubmit the idle work)
- cancel the idle work (so that it does not schedule and re-set the
interrupt or timers)
- disable interrupts (if used)
- stop the sampling timer
- disconnect the pins
The resume sequence is more or less the opposite.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Some devices like S32K1xx don't feature an internal 32.768 KHz
oscillator. Also, updated the code to use the existing HAL API
for this purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
These changes enable -
1. S32 gmac driver to gracefully handle
net iface down and up net shell commands and
2. Link connect or disconnect events between
Ethernet PHY and its link partner.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Currently, whenever performing TRIGGER_PAUSE operation, the
data line is not disabled. This works well if TX and RX don't
operate at the same time or they operate in ASYNC-ASYNC mode. This
is because sai_tx_rx_disable() will disable transmitter/receiver
all the time since there's no dependencies to take into consideration.
However, in the ASYNC-SYNC mode, sai_tx_rx_disable() may not disable
the current asynchronous side if the synchronous side is still enabled.
As a consequence, the asynchronous side will remain enabled, thus
leading to an underrun/overrun.
To fix this issue, sai_trigger_pause() should disable the data line
each time it's called. This way, even if sai_tx_rx_disable() doesn't
disable the current direction, the data line will be disabled, thus
stopping the consumption/production of frames.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Supurious interrupts can be generated when the SPI device
is disabled. Ignore them within the SPI IRQ handler.
Co-authored-by: Georgij Cernysiov <geo.cgv@gmail.com>
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Allow to use H7 SPI FIFO to improve performance.
SPI FIFO usage can be enabled/disabled from devicetree.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Set the transfer size in SPI H7 and check EOT instead of TXC
to be sure the transaction has finished. This is required to
enable the use of the SPI FIFO, as otherwise SPI seems to
operate in "continuous mode", which produces several SCK cycles
after the last frame has been sent/received. More details in the PR.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
In many cases suspending or resuming of a device is limited to
just a few register writes. Current solution assumes that those
operations may be blocking, asynchronous and take a lot of time.
Due to this assumption runtime PM API cannot be effectively used
from the interrupt context. Zephyr has few driver APIs which
can be used from an interrupt context and now use of runtime PM
is limited in those cases.
Patch introduces a new type of PM device - synchronous PM. If
device is specified as capable of synchronous PM operations then
device runtime getting and putting is executed in the critical
section. In that case, runtime API can be used from an interrupt
context. Additionally, this approach reduces RAM needed for
PM device (104 -> 20 bytes of RAM on ARM Cortex-M).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add cleanups to pin presence checks within the mipi_dbi SPI driver.
The cleanups now verify that GPIO and RESET pin devices are ready,
if they are present for the device instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use a delegate for reporting the core clock rate of the fake CAN
driver. This allows overriding the delegate at run-time and inspecting its
call count.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Promote clk_ratio_adj to double for internal calculations related to ratio
to avoid compilation warnings related to implicit conversion from float
to double.
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
This adds support for the GRLIB SPIMCTRL SPI controller used in LEON and
NOEL-V systems. SPIMCTRL can operate in two different modes: In the
default mode it allows memory-mapped read access to the flash data. When
set in the user mode, it can be used to generate SPI bus transactions.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Support SFDP probe in flexspi nor driver. This probe will allow the
flash driver to dynamically configure quad spi flashes for 1-4-4 mode,
expanding the flash chips supported with this driver.
The following data is read from the SFDP header:
- quad enable method
- fast read command (1-4-4 is maximum supported)
Fixes#55379
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking flexspi in ccm_rev2 driver. Clock update
functions are provided for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
