The clock should be initialised only once at the
drivers init function.
Check wether the subsys needs to be disabled in
peripheral initialization according to reset reason
in clock control.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add API to perform hardware reset optionally entering firmware updater
mode.
Remove redundant declaration for bt_spi_send_aci_config; otherwise, we will
have compiler warning if CONFIG_BT_BLUENRG_ACI is not set.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Found via static analysis. Two separate error paths where failing to
check the return code leads to undefined behavior:
1. In `litex_clk_get_phase`, the divider stays set to 0 when
`litex_clk_get_clkout_divider` errors out, which leads to a division
by 0.
2. In `litex_clk_calc_duty_normal`, the `duty` struct is used
uninitialized if `litex_clk_get_duty_cycle` errors out.
In both case, checking the return code and returning early resolves the
issue.
Signed-off-by: François Baldassari <francois@memfault.com>
Use BLE.ADDR to create unique (to some extent) EUI64
on nRF54H20 in some cases inside the IEEE 802.15.4 driver.
The amount of EUI64-s available in such a way is very limited
(~16 million).
However, currently there does not seem to be another feasible way to
get device identifiers on nRF54H20 (such are kept in SICR, to which the
radio core has no access).
Signed-off-by: Piotr Koziar <piotr.koziar@nordicsemi.no>
Move STM32_MEMMAP outside of SOC_FLASH_STM32.
That allows memory-mapped application to
be built without internal flash controller.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This commit should deal with adding a missing
direction case as memory-to-peripheral
and peripheral-to-memory transfers
should be considered the same.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
When low power mode is enabled then whenever UARTE is not active,
driver attempts to put the peripheral into the lowest power state
by stopping and disabling UARTE. However, it did not put pins into
sleep state which could lead to increased current consumption.
Adding pins state handling to the low power mode.
Pins are put into sleep state only if CONFIG_PM_DEVICE=y.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
In function pcal64xxa_process_input, lock was not released in case of
error when calling inputs_read.
This was causing an infinite wait in the following calls of functions
using I2C bus.
Signed-off-by: Vincent Geneves <vgeneves@kalray.eu>
Add DISK_IOCTL_CTRL_DEINIT ioctl command to disk subsystem. When
disk_access_ioctl() is called with this command, the disk will be
de-initialized. After this IOCTL completes, the disk can safely be
reinitialized.
Fixes#60628
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add DISK_IOCTL_CTRL_INIT IOCTL to initialize a disk. This IOCTL is
intended to replace disk_access_init() for new applications, but
disk_access_init() is kept for legacy compatibility. The INIT IOCTL is
added to better match the path that will be used for disk
de-initialization. Like the disk_access_init() calls,
DISK_IOCTL_CTRL_INIT calls are reference counted
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Reference count initialization calls for disks. This changes the
behavior of the disk_access_init() function, such that disks will no
longer be initialized again if the first disk access init call
succeeds.
Disk access is reference counted in preparation for supporting disk
de-initialization, where a balanced number of disk de-initialization
calls with disk initialization calls will de-initialize the disk.
Also, remove code in disk drivers that was already checking against
duplicate disk_access_init() calls.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Align the name of the ETH PTP Config Status values
depending on the stm32HAL serie
to be the HAL_ETH_PTP_NOT_CONFIGURATED/HAL_ETH_PTP_CONFIGURATED
or HAL_ETH_PTP_NOT_CONFIGURED/HAL_ETH_PTP_CONFIGURED
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add driver for Realtek RTL8211F 10/100/1000M ethernet PHY.
This driver implements vendor specific behaviour like
detecting link state change by GPIO interrupt, which is not
present in the generic MII driver.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
- Added nxp,enet1g compatible to distinguish between ENET (nxp,enet)
and ENET_1G (nxp,enet1g) peripherals within the same driver.
- Added config ETH_NXP_ENET_1G to enable 1G mode of operation on ENET_1G.
- Support RGMII mode of connection between MDIO and PHY to be
able to work with ENET_1G peripheral and support 1000M speed.
- Removed performing of PHY reset before configuring link - it is
not desirable for RTL8211F PHY connected to ENET_1G on RT1170.
Reset of other PHYs can be performed by PHY driver itself if required.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add ENET_1G clock value to the RT11XX CCM version.
Implemented enabling ENET_1G clock and getting its frequency.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Introduce driver for ov7670 camera, supporting QCIF,QVGA,CIF, and VGA
resolution in YUV and RGB mode.
Support was verified on the FRDM-MCXN947, using the SmartDMA camera
engine, which is enabled in the following PR:
https://github.com/zephyrproject-rtos/zephyr/pull/72827
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This reverts commit 99aa65c725.
With this change, various simulators fail with no output with this
change.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Configure the quad-spi in DualFlash Mode when enabling the MemoryMapped
then reading is possible with memcopy.
DUAL flash mode is possible on stm32 series with QUADSPI_CR_DFM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use poll() to wait for connect attempt to complete or timeout. That way
connect() does not block Native Simulator on host syscall.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
So far only a single blocking API could be handled simultaneously, due to
epoll_ctl(..., EPOLL_CTL_ADD, ...) returning -EEXIST when same file
descriptor was added twice.
Follow 'man epoll' advice about using dup() syscall to create a duplicate
file descriptor, which can be used with different events masks. Use such
duplicate for each blocking API except ioctl() (for handling Zephyr poll()
syscall).
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Introduce nsos_poll_if_blocking(), which replaces common code in:
* nsos_accept_with_poll()
* nsos_recvfrom_with_poll()
This will allow to introduce similar behavior for other blocking APIs in
subsequent commits.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
On nRF54H20DK the USB PHY is powered from VBUS. When the USB cable is
not connected, the PHY is not powered and the PHY clock disappears.
Because the GOUTNAKEFF and INEPNAKEFF can only ever be set when PHY
clock is active, the waits for these bits do timeout if cable is
disconnected. Workaround the issue by aborting the wait if vendor quirk
indicates that PHY clock has abruptly vanished.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The original driver has two defects: 1. When setting the next timeout
value the original implementation simply sets a delta value equal to
ticks * CYC_PER_TICK. This operation is reckless and may incorrectly
"reset" the fractional tick, causing clock skew. 2. The original
implementation doesn't handle the counter overflow situation. When the
counter overflows from 0xffffffff to 0x0, the uptimer counter becomes
incorrect. We have fixed above issue by rewriting most of the functions in
this driver and verified it by running all tests under
tests/kernel/timer folder.
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
As far as I can tell it appears that the hardware
does not support acceleration of ICMPV6 checksums.
For now, the easiest way to fix the runtime failure of
IPV6 is just to disable the hardware acceleration if
IPV6 is expected to be used.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Moves the rtio_ prefixed lockfree queues to sys alongside existing
mpsc/spsc pbuf, ringbuf, and similar queue-like data structures.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Introduce the stm32h7RS serie to the gpio driver,
based on the stm32h7
The SBS controller is used to configure the EXTI line among
the different GPIO port.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce the stm32h7RS serie to the pin control driver,
New GPIO port M, N, O, P
Then add the complete list and from A to P (16 port
coded on 5 bits)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce the stm32h7RS serie to the clock_controller,
based on the stm32h7 clock driver
Datasheet DS14359 rev 1 gives CPU max freq of 500MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Calculate and set a proper Transceiver Delay Compensation Offset (TDCO)
based on FlexCAN FD timing.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Introduce a custom STM32_GPIO_WKUP GPIO flag.
Use the newly introduced stm32_pwr_wkup_pin_cfg_gpio() public
function to configure GPIO pins, that have the STM32_GPIO_WKUP
flag in DT, as sources for STM32 PWR wake-up pins, on the condition
that there is a wake-up pin that corresponds to each of them.
These GPIO pins can then be used to power on the system after Poweroff
like a reset pin.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Rename the "bus_speed" and "bus_speed_data" fields of struct
can_driver_config to "bitrate" and "bitrate_data" to match the
corresponding devicetree properties and the terminology used in the rest of
the CAN subsystem API.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Deprecate the CAN controller bus-speed/bus-speed-data properties and rename
them to bitrate/bitrate-data to match the terminology used in other CAN
devicetree properties and the CAN subsystem API.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
SPIM12x instances can perform DMA only from memory region
that is cacheable by default.
SPIM12x instances pins are configured via CTRLSEL mechanism,
which prevents the GPIO registers from ensuring correct bus
state when peripheral does not drive the bus lines.
External configuration of SPIM12x ENABLE register fixes this issue.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
