Andes MBOX PLIC-SW use the same hardware as intc_plic driver. Reworked
mbox_andes_plic_sw implementation to leverage the intc_plic driver.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The ILPS22QS is an ultra-compact piezoresistive absolute pressure sensor
which functions as a digital output barometer, supporting dual full-scale
up to user- selectable 4060 hPa. The device delivers ultra-low pressure
noise with very low power consumption and operates over an extended
temperature range from -40 °C to +105 °C.
(https://www.st.com/en/mems-and-sensors/ilps22qs.html)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add a generic lps2xdf_config_int() API to configure device interrupt
mode, and implement the specific routines for lps22df and lps28dfw.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Move api_lps2xdf_handle_interrupt() API inside the CONFIG_LPS2XDF_TRIGGER
ifdef, because it should be defined only in that case.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
DWC2 peripherals can have TxFIFO sizes configured to any value between
16 and 32768. The value configured during synthesis is the maximum value
the software can program. Designs that give full flexibility configure
the TxFIFO sizes to value equal to total SPRAM size.
Currently DWC2 driver does not have prior knowledge about the endpoints
used within available configurations and has to come up with TxFIFO0
value up front. The original approach was to use MAX(16, max allowed).
locations. Because DWC2 peripheral cannot have TxFIFO0 with size lower
than 16 locations, always the max allowed was used. This logic prevented
any IN endpoint other than EP0 on designs that have TxFIFO0 size set to
total SPRAM size.
Change the logic to MIN(2 * 16, max allowed) to have sufficient memory
available on flexible designs and allow simultaneous operation if
possible (i.e. when maximum TxFIFO0 size is at least 32).
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
DWC2 otg OUT transfers are being used for SETUP DATA0, OUT Data Stage
packets and OUT Status Stage ZLP. On High-Speed it is possible for IN
Data Stage, OUT Status Stage ZLP and subsequent SETUP DATA0 to happen
in very quick succession, making all the three events appear at the same
time to the handler thread.
The handler thread is picking up next endpoint to handle based on the
least significant bit set. When OUT endpoints were on bits 0-15 and IN
endpoints were on bits 16-31, the least significant bit policy favored
OUT endpoints over IN endpoints. This caused problems in Completer mode
(but suprisingly not in Buffer DMA mode) that lead to incorrect control
transfer handling.
The choice between least significant bit first or most significant bit
first is arbitrary. Switching from least to most significant bit first
would have resolved the issue. It would also favor higher numbered
endpoints over lower numbered endpoints.
Swap the order of endpoints in bitmaps to have IN on bits 0-15 and OUT
on bits 16-31 to keep handling lower numbered endpoints first and
resolve the control transfer handling in Completer mode.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Rename the Silabs HCI driver to hci_silabs_efr32.c to better indicate what
hardware it supports. Also rename the associated devicetree binding and
Kconfig options to be consistent with the new driver name.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The default configuration for PINCTRL should not be set with
the other default configurations in .defconfig, instead select
a default value as part of defining the UART driver.
Signed-off-by: Andrew Davis <afd@ti.com>
DT_INST* should be used in MSPI_CONFIG or device tree value capture
will fail sliently and fall back to defaults.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
This commit does the following:
1. tests set_callback and user_data
2. fixes the api as well as the drivers by passing user_data
back to the set callback
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
IS25LP flash chips have a similar P[6:3] register to the IS25WP series,
and need the same workaround.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some NXP boards program the read parameters bits (P[6:3]) within the
IS25WP flash device during init, which will result in JESD216 probe
commands failing (as the number of dummy cycles will be incorrect). Add
handling to force these volatile bits to their default value to the
flexspi flash driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Quad enable method 5 reads status register 2 (one byte), but then writes
to 2 bytes to the status registers, so we need to shift the output
buffer in order to manage this correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Writing the quad enable bit on flash chips typically requires a write
enable instruction be issued before writing the non-volatile status
register, and the flash may remain busy briefly after programming this
bit. Add code to send the WREN instruction, and to wait for the flash to
finish programming after writing the status register.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move the LUT used for probing to be stored in .data, instead of on the
stack. This reduces stack usage during probe by 192 bytes, which avoids
stack overflows that were occurring on some platforms.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Even in cases where the alt-addr is set, we can still use the INT pin
during probe. Some boards require this, as if a reset GPIO is not
defined the INT pin may still need to be toggled in order to initialize
the GT911 IC correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Following similar approach followed on spi_mcux_lpspi driver.
- Enabling DMA by default when SPI RTIO is selected to favor
non-blocking transfers.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Updated ADXL372 driver with RTIO stream functionality.
RTIO stream is using both FIFO threshold and FIFO full triggers.
Together with RTIO stream, RTIO async read is also implemented.
Signed-off-by: Vladislav Pejic <vladislav.pejic@orioninc.com>
Some instances of the FLEXSPI IP permit limiting AHB bus access so that
no memory access requests will straddle a page boundary. Add a property
to manage this setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
is66wvq8m4 PSRAM always requires the address to be left shifted by
5 bits, regardless of which FLEXSPI port it is on. Fix the addressShift
assignment to be unconditional
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The ADDRSHIFT bit simply left shifts the address written to IPCR0[SFAR],
(or the address used for AHB access), by 5 bits before sending it to the
attached memory. This bit does not have an effect on the base address
used to access the flash/psram device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Transactions from RTIO should result in single calls to i2c_transfer.
This corrects the default handler to first count the number of
submissions in the transaction, allocate on the stack, and then copy
over each submission to an equivalent i2c_msg.
It also cleans up the helper functions to be infallible, taking only the
submission and msg to copy to.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
TXRX is meant specifically to handle a full duplex bus like SPI, I2C is
half duplex meaning only read or write can be performed at once.
Drop TXRX as a supported operation code for the default I2C submission
path.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Updated ADXL345 driver with RTIO stream functionality.
Added Trigger intterupt functionality. RTIO stream is using
FIFO threshold.Together with RTIO stream, RTIO async read
is also implemented.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Implements the SPIO RTIO API. Refactors internal transcive
fucntios to work with both existing SPI API and RTIO functions.
When SPI_RTIO is enabled the spi_transcieve call translates
the request into an RTIO transaction placed in the queue
that device will execute.
Include the latest refacor changes of RTIO.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Function dma_smartbond_set_channel_status() used incorrect
condition to release state lock.
In initialization function dma_smartbond_init() function
dma_smartbond_set_channel_status() was called for each DMA
channel and tried to release lock that was never taken.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Timer driver using Microchip 32KHz based RTOS timer as the kernel
timer tick. The driver uses one of the 32-bit basic timers to
support the kernel's k_busy_wait API which is passed a wait
count in 1 us units. The 32-bit basic timer is selected by using
device tree chosen rtimer-busy-wait-timer set to the handle
of the desired 32-bit basic timer. If this driver is disabled,
the build system will select the ARM Cortex-M4 SysTick as the
kernel timer tick driver. The user should specify RTOS timer
as kernel tick by adding the compatible properity and setting
the status property to "okay" at the board or application level
device tree. The driver implements two internal API's for use
by the SoC PM. These two API's allow the SoC PM layer to disable
the timer used for k_busy_wait so the PLL can be disabled in
deep sleep. We used a custom API so we can disable this timer
in the deep sleep path when we know k_busy_wait will not be
called by other drivers or applications.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Use DT_*IRQN helper to get the IRQ number on systems with multi-level
interrupt configuration instead of IRQ number on particular interrupt
controller.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Though nRF7000 is a special Scan only chipset, scan only can work with
any nRF70 platforms, no need for this enforcement and we can keep things
flexible.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
The ieee802154_nrf5 supports the IEEE802154_SELECTIVE_TXCHANNEL
Kconfig option and advertises the IEEE802154_HW_SELECTIVE_TXCHANNEL
capability.
The ieee802154_nrf5 driver now allows to schedule timed transmission
requests with selective tx channel, that is set at the latest
possible moment. This improves reception performance when the
timed transmissions are requested.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
The Kconfig `IEEE802154_SELECTIVE_TXCHANNEL` is added along with
the new capability `IEEE802154_HW_SELECTIVE_TXCHANNEL`.
The new capability of the ieee802154 drivers allows to schedule
CSL transmissions as stated in IEEE 802.15.4-2020 chapter 6.12.2.7
CSL over multiple channels. The benefit of the new API is that
additional call to `ieee802154_radio_api::set_channel()` is not
required. The drivers will switch to the new channel as late as
possible for CSL transmissions thus will not interrupt any reception
that might be in progress until the very late moment when the
transmission actually starts.
This improves reception performance when CSL transmissions are used.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Add wsen_hids_2525020210002 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
Updated ADXL362 driver with RTIO stream functionality.
RTIO stream is using both FIFO threshold and FIFO full triggers.
Together with RTIO stream, RTIO async read is also implemented.
Signed-off-by: Vladislav Pejic <vladislav.pejic@orioninc.com>
