Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some headers made use of types defined in sys_clock.h (e.g. k_timeout_t)
without including it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files using time_units.h API did not include it, e.g. for
sys_clock_hw_cycles_per_sec.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It is better to use 64-bit variable types for calculating the number
of elapsed ticks than 32-bit variable types. This guards against the
propagation of calculation errors should the lower 32-bits of the timer
counter roll over multiple times before the timer ISR is serviced.
(Such a scenario can easily occur when pausing the system for an
extended period of time with a debugging device such as a Lauterbach.)
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
A specific check is implemented lptim driver in order to ensure global
platform clock/tick configuration is in line with recommendations.
To respect portability principles, don't error out when a config
conflict is detected but generates a warning instead.
Also, since these are only recommendations, provide an option to override
the check. Besides automatically override when ZTEST is enabled, as some
kernel tests specifically configure tick freq to 100.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In some configurations, a udf instruction may be generated
when compiling code where static global variable lptim_clock_freq is
used as a divisor.
To avoid this, initialize variable on declaration so that compiler
could see that it can't be used uninitialized in this division.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
On L0 series, LSI runs at 37KHz while LPTIM driver only supports speeds
up to 32768Hz (to avoid counter overflow). Consequence is a time running
faster than reality (x1.13)
Solution to this is the implementation of the LPTIM prescaler support.
While moving driver configuration from Kconfig to DT, this case was
not taken into account and the effect was LPTIM counter overflow which
consequence is worse than the slightly faster timer.
Reproduce the initial behavior with this piece of code that will be
removed once prescaler support is available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When using LPTIM as tick source, tick freq (SYS_CLOCK_TICKS_PER_SEC)
needs to be adapted to get a precise tick to LPTIM freq ratio.
This adaptation was done easily using Kconfig up to now (under
soc/st_stm32/common/Kconfig.defconfig.series).
Since driver is configured using device tree, this method should
be adapted. For the LSI case (default Kconfig case), rely on the
existing mecanism, which is also still used by OOT users.
For the LSE case, force the value manually in boards forlder.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following transition of lptim timer configuration from Kconfig to DT,
a warning message was set to inform users about this deprecation.
Due to errors in CI this message had to be removed while fixing the related
issues.
Now these issues are fixed, set the deprecation message again.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Similarly to other drivers, use auto generated DT_HAS_<COMPAT> Kconfig
symbol to control use of STM32 lptim driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
west.yml: update hal_espressif to use latest v4.4.1 updates.
This change needs to be insync with esp32c3 timer changes, otherwise it
breaks it.
drivers: timer: update esp32c3 systimer to meet API changes.
Systimer API was refactored in hal v4.4.1, which
requires updates in esp32C3 systimer. Timer behavior is maintained
as is.
mcpwm: add v4.4.1 include reference, which was refactored as well.
driver: spi: esp32: update internal structs to meet API changes.
cmake: updated esp32 board to use HAL_ prefix as from west blobs
requirement.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Increase the default user-allocable number of RTC channels to meet
the nrf_802154 driver requirements.
Signed-off-by: Adam Zelik <adam.zelik@nordicsemi.no>
It is frequent to find variable definitions like this:
```c
static const struct device *dev = DEVICE_DT_GET(...)
```
That is, module level variables that are statically initialized with a
device reference. Such value is, in most cases, never changed meaning
the variable can also be declared as const (immutable). This patch
constifies all such cases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It appears that some in tree boards still enable lptim w/o configured
domain clocks.
Remove this deprecation message the time a clean up is done fully.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of relying on Kconfig, use dt inputs to configure LPTIM domain
clck (LSI/lSE).
Clock control dedicated APIs are used for configuration and get the
frequency of domain clock in use.
Constants macros used previously to store frequency and time base are
converted to static global variables.
Some code was set up specifically to keep compatibility with targets
that still use Kconfig to configure domain clock. This will be removed
after a deprecation period.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Continue conversion of LPTIM driver to device tree based configuration.
Get clock configuration from device tree and use clock_control API for
bus clock configuration
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Start converting LPTIM driver to device tree based configuration and
support of other instances.
First: get base address and IRQ using dt instance
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
IRQ7 is placed on the second element of interrupt definition.
Select it by DT_INST_IRQ_BY_IDX() explicitly.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The waiting of the flag ARROK could be quite long (100µs-200µs in my
test). During this time, the interrupts are locked that is not
recommended. To avoid this, we manage the update of the autoreload value
in interruption
Signed-off-by: Julien D'Ascenzio <julien.dascenzio@paratronic.fr>
This commit fixes the incomplete assert conditions for the `chan`
argument passed to the nRF RTC timer functions.
Note that the `chan` argument for this driver is of a **signed**
integer type, so it is necessary to check that its value is
non-negative.
This fixes the warnings generated by the GCC 12 such as:
error: array subscript -1 is below array bounds of '...'
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Use Devicetree to describe secure timer0 instead of hardcoding values in
<soc.h>.
DT files have been structured to match the following requirements: In
case of sectimer0 - it's should be only enabled for:
- emsdp_em7d_esp.dts
- em_starterkit_em7d.dts
- nsim_sem_mpu_stack_guard.dts
- nsim_sem.dts
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Obtain machine timer addresses and IRQ from Devicetree. Note that driver
supports multiple compatibles because mtime/mtimecmp registers are
implemented in different ways depending on the vendor. That means
Devicetree representations can be slightly different and so code to
collect the information needs to treat each compatible differently.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Declare clock control in the shim header per SoC and remove ifdeffry
from the driver simplifiying it and making it ready for the next
platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
using once single header to support multiple socs and product
generations is error prone and not easily maintained.
Over time we have been adding conditional code in headers and extending
structs to support new HW features which becomes a problem.
Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.
This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
When using the APIC imer in TSC deadline mode, also enable reading the
full 64-bit cycle counter value (via the k_cycle_get_64() call).
Signed-off-by: Bruno Achauer <bruno.achauer@intel.com>
Not all platforms support setting the LSE driving capability, causing
the build to fail for platform such as the STM32L072 if compiled with
CONFIG_STM32_LPTIM_CLOCK_LSE=y.
Adding an #ifdef guard around the call to skip it if not defined in the
HAL.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add timer driver based on CAVS driver and adapted for Meteor Lake.
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As with previous commit, make the timer irq a simple integer variable
exported by the timer driver for the benefit of this one test
(tests/kernel/context).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This test has gotten out of control. It has a giant #if cascade
enumerating every timer driver in the Zephyr tree and extracting its
interrupt number. Which means that every driver needs to somehow
expose that interrupt in its platform headers or some other API.
Make it a simple integer variable exported by the timer driver for the
benefit of this one test.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On FVP platform, when parameter 'bp.refcounter.use_real_time' is set
to 1, cntvct_el0 isn't count from 0 and may cause overflow issue in
first timer compare interrupt.
'bp.refcounter.use_real_time' is 0 by default.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Fast hardware with slow timer hardware can trigger and enter an
interrupt and reach 'sys_clock_set_timeout' before the counter has
advanced.
That defeats the "round up" logic such that we end up scheduling
timeouts a tick too soon (e.g. if the kernel requests an interrupt
at the "X" tick, we would end up computing a comparator value
representing the "X-1" tick!).
Choose the bigger one between 1 and "curr_cycle - last_cycle" to
correct.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue
The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.
The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.
The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
e8e88dea incorrectly changed registers
used in `sys_clock_cycle_get(32|64)` functions.
This commit fixes that.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds addresses and names for individual CSR registers to device tree.
This way timer driver no longer depends on CSR data width being 8 bits.
Also when register names their number changes, then overlay generated by
LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also updated register names to those used in current LiteX and
appended `_ADDR` suffix to defines which lacked them.
Because register `total` was renamed to `value` and `update_total` to
`update_value` I updated variables accordingly as well.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Use LiteX HAL functions instead of `sys_read*` or `sys_write*`
functions.
They use them inside, but choose which one to use according to
configured CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Setting event timer count at least 1 hw count, it's redundant,
so I clean up this else {} case. And add the comment about
the K_TICKS_FOREVER and INT_MAX case.
NOTE:
CONFIG_TIMEOUT_64BIT = y, then k_ticks_t type is int64_t.
K_FOREVER is (k_timeout_t) { .ticks = (K_TICKS_FOREVER) },
and K_TICKS_FOREVER is ((k_ticks_t) -1),
so K_FOREVER is a k_timeout_t type structure, and
the member ticks: type int64_t,
value (= K_TICKS_FOREVER) 0xFFFF FFFF FFFF FFFF.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
ITE RTOS timer HW frequency is fixed at 32768Hz, because this
clock source is always active in any EC mode (running/doze/deep doze).
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
We don't need to convert the free run clock count,
that will be converted by the kernel
(base on CONFIG_SYS_CLOCK_TICKS_PER_SEC),
so we should return the HW register count value directly.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The function npcx_clock_get_sleep_ticks is currently guarded by
CONFIG_PM && CONFIG_NPCX_PM_TRACE. The other codes guarded by
CONFIG_NPCX_PM_TRACE is used to trace and will print a lot of messages.
The user who wants to use npcx_clock_get_sleep_ticks has to enable this
flag and get a lot of console spam. This commit removes the guard
CONFIG_NPCX_PM_TRACE and makes this function is available when
CONFIG_PM is defined.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
There wasn't the build error in PR#44060,
but now tool chain isn't happy about putting the arch_busy_wait()
to __ram_code section, then it shows a build error:
https://github.com/zephyrproject-rtos/zephyr/runs/5755633537?check_suite_focus=true#step:10:933
So I remove __ram_code of arch_busy_wait(), and this will need
extra fetch code time when arch_busy_wait() code isn't in
the dynamic cache.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/drivers/flash
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Customize busy wait timer for micro-seconds accuracy.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
west build -p auto -b it8xxx2_evb tests/drivers/adc/adc_api
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This add support to pinctrl at Atmel sam0 rtc driver. It allows to
define pins to be used for tamper detection.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Do not use __disable_irq when Zero Latency IRQs are enabled
and the Zephyr open source Bluetooth Controller is used with
Zero Latency IRQs support.
Application shall ensure their Zero Latency IRQ ISRs do not
invoke any kernel APIs.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add an explicit Kconfig option to enable use of
__disable_irq() in nRF RTC timer driver to prevent higher
priority contexts (including ZLIs) that might preempt the
handler and call nrf_rtc_timer API from destroying the
internal state in nrf_rtc_timer.
Relates to commit fcda8699cb ("drivers: timer: extend
nrf_rtc_timer").
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Re-running the script that checks for the const qualifier missing on
struct device ISR's parameter.
The script also changes the parameter 'arg' to 'dev' when relevant.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Indirect ISR automatically calls power management functions, which GPT
timer direct ISR was not calling. Calling these functions means that the
kernel will recognize that it is exiting low power mode when the GPT
timer interrupt fires that wakes the SOC up, and will call
pm_power_state_exit_post_ops, which can in turn raise the clock
frequencies and voltage of the SOC as early as possible.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The RTC user channel count is increased contitionally to 2 when
nrf_802154 radio driver is enabled.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Rename CONFIG_SOC_POWER_MANAGEMENT_TRACE to CONFIG_NPCX_PM_TRACE so that
it is clear that it's a NPCX specific option.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Increase the default user-allocable number of RTC channels to 3,
which is the numer of physical RTC CC channels not used by Zephyr
on nRF52 series SoCs.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Use index zero, not one. The Xtensa tools emit the timers in priority
order, and as mentioned in the kconfig warnings using high priority
timers doesn't work. This also makes room for using software
interrupts that can preempt a timer interrupt for test purposes.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
GPT timer driver was announcing progress to the kernel too soon when an
announcement was requested via sys_clock_set_timeout() on a tick
boundary. Fix rounding to add a tick worth of cycles.
Fixes#42665
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit adds support for tickless operation on the MIPS CP0 timer.
The code closely follows the Xtensa and RISCV timer drivers.
All tests pass.
Signed-off-by: Remy Luisant <remy@luisant.ca>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
GPT timer must continue running in low power modes, as it is the system
wakeup source. Set configuration to ensure peripheral will not stop
running in low power modes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
On some platforms, HPET is not wired to trigger IRQ 2.
This would make HPET non-functional if the legacy
interrupt routing bit is set in the global config
register. This adds a DTS flag so the driver won't
set the bit to enable legacy interrupt.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
General refactoring to clean up and futureproof this driver.
Remove false dependency on CONFIG_CAVS_ICTL. This requires the CAVS
interrupt mask API, but doesn't touch the interrupt controller driver.
Remove a racy check for simultaneous interrupts. This seems to have
been well intentioned, but it's needless: the spinlock around the
last_count computation guarantees that colliding interrupts will
correctly compute elapsed ticks (i.e. the last will compute and
announce zero ticks, which is correct and expected). And this opened
a tiny window where you could incorrectly ignore a just-set timeout.
Factor out the specific registers used (there are only five) into
pointer-valued macros instead of banging them directly.
Unify interrupt initialization for main and auxiliary cores.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
In npcx_itim_evt_isr, it updates the cyc_sys_announced variable and
then calls sys_clock_announce() to update the kernel curr_tick variable.
If an ISR handler with higher priority preempts the timer ISR after the
sys_clock_announce is updated and before the sys_clock_announce() is
called, it will read the wrong time when calling k_uptime_get() because
the cyc_sys_announced and the curr_tick are not synchronized.
The commit fixes the problem by raising the timer's interrupt priority
to the highest one (i.e. 1 in npcx's configuration).
This commit also moves the computation of the delta cycle inside the
spinlock in sys_clock_elapsed() to prevent another potential racing
condition.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This commit introduces the following changes:
* nrf_rtc_timer is extended with a capability to handle RTC overflow,
allowing it to operate on absolute RTC ticks, rather than relative
ticks.
* overflow handling is ZLI-proof and relies on the sys clock
handler being executed twice every RTC counter's overflow.
* callbacks are given an absolute RTC tick value as a parameter instead
of CC register's value. The absolute RTC tick value is the RTC counter
value set during CC channel configuration extended to 64 bits.
* in case the timer's target time is in the past or is the current tick,
the timer fires as soon as possible, however still from the RTC's ISR
context.
* in case an active timer is set again with the same target time, it is
not scheduled again - only its event data is updated. Otherwise, the
timer is scheduled as usual.
* a scheduled timer can be aborted.
* system clock functions are now using 64 bit values internally.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Signed-off-by: Paweł Kwiek <pawel.kwiek@nordicsemi.no>
GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit introduces the following changes:
* nrf_rtc_timer is extended with a capability to handle RTC overflow,
allowing it to operate on absolute RTC ticks, rather than relative
ticks.
* overflow handling is ZLI-proof and relies on the sys clock
handler being executed twice every RTC counter's overflow.
* callbacks are given an absolute RTC tick value as a parameter instead
of CC register's value. The absolute RTC tick value is the RTC counter
value set during CC channel configuration extended to 64 bits.
* in case the timer's target time is in the past or is the current tick,
the timer fires as soon as possible, however still from the RTC's ISR
context.
* in case an active timer is set again with the same target time, it is
not scheduled again - only its event data is updated. Otherwise, the
timer is scheduled as usual.
* a scheduled timer can be aborted.
* system clock functions are now using 64 bit values internally.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Signed-off-by: Paweł Kwiek <pawel.kwiek@nordicsemi.no>
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The init responsibility moves to the drivers themselves. The npcx itim
initialize doesn't work now. This adds timer initialization for npcx
itim to fix it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
A couple of drivers violated MISRA 5.7 rule (Tag name should be unique),
triggering CI compliance errors.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
A Cortex-M specific function (sys_clock_isr()) was defined as a weak
function, so in practice it was always available when system clock was
enabled, even if no Cortex-M systick was available. This patch
introduces an auxiliary Kconfig option that, when selected, the ISR
function gets installed. External SysTick drivers can also make use of
this function, thus achieving the same functionality offered today but
in a cleaner way.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- Remove the weak symbol definition
- Notify about the capability of disabling via a selected Kconfig option
(CONFIG_SYSTEM_TIMER_HAS_DISABLE_SUPPORT)
- Provide a dummy inline function when the functionality is not
available
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Split Kconfig into individual files for each driver. This improves
overall readability of the Kconfig options.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The weak symbol sys_clock_driver_init has been removed, therefore moving
the init responsability to the drivers themselves. As a result, the init
function has now been made static on all drivers and moved to the
bottom, following the convention used in other areas.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions. This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.
Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.
Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block. Those will be unified in separate
patches.
Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Recent work to this platform added a new, cleaner low level API to the
interrupt controller. Replace the hand-cooked register access with
that. This is still not as good as having proper multicore support in
the intc_cavs driver, but it's at least better.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Clock ISR was running 2x the frequency.
Also fixes clock_get_cycle which was returning
wrong values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The macro already mentions in the docstrings that PM is not supported:
"Invokes DEVICE_DEFINE() with no power management support".
This patch removed the PM entry from the macro and ajusts its uses.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In commit 918a574c88 ("clock: add k_cycle_get_64") this driver was
augmented with a count64() method to get a 64 bit cycle output from
the two-32-bit-word device registers.
Unfortunately it appeared to be trying to use a spinlock around the
two (low/high) reads to protect against overflow. But that doesn't
work: spinlocks protect against other CPU code using the same
spinlock, not against a hardware counter that is incrementing in real
time!
Thankfully there was already a count() routine in place that does a
detect-overflow-and-retry loop to solve this. Use that.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This change adds `k_cycle_get_64()` on platforms that
support a 64-bit cycle counter.
The interface functions `arch_k_cycle_get_64()` and
`sys_clock_cycle_get_64()` are also introduced.
Fixes#39934
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Modification of the ARM architected timer driver and its configuration
data in order to address an erratum which exists at least in the Cor-
tex-A9 CPU, and which can also be observed in the QEMU implementation
of the Cortex-A9.
Comp.: ARM Cortex-A9 processors Software Developer Errata Notice
ARM document ID032315
Erratum 740657
This erratum causes a spurious interrupt pending indication with the
interrupt controller if no new compare value is written within the
timer ISR before the interrupt is cleared. This is usually the case
in tickless mode. If the spurious interrupt is not prevented, the
timer ISR will be called twice, but on second execution, the pending
flag is not set within the timer's register space. Not handling this
issue will lead to erratic tick announcements to the kernel.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
With the introduction of `EXPERIMENTAL` and `WARN_EXPERIMENTAL` in
Zephyr all drivers settings having `[EXPERIMENTAL]` in their
prompt has has been updated to include `select EXPERIMENTAL` so that
developers can enable warnings when experimental features are enabled.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Timer STM32 LPTIM currently supports 2 clocks sources: LSE & LSI.
LSE (external) is defined as default but its availability depends
on board support package and then may not be available.
This ends up in situations where users have LSE implicitly selected
while no crystal is available on board, leading to non functional
LPTIM.
To avoid this situation, makes LSI clock, which is always available
(since internal to the SoC), the default LPTIM source clock.
Then, default case will be functional. Users will then be able to
select LSE if needed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
When SMP is enabled all the cores are announcing a tick and this is
causing too many ticks to be announced. Announce the tick even if this
is zero.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
If CYC_PER_TICK does not divide the (now - last_count) quantity exactly with integer math, the subsequent multiplication before incrementing last_count causes a drift. This commit eliminates the redundant division-followed-by-multiplication and fixes https://github.com/zephyrproject-rtos/zephyr/issues/37852
Signed-off-by: Berend Ozceri <berend@recogni.com>
This function wasn't being defined when SMP_BOOT_DELAY was set or when
SMP wasn't enabled. There's no reason for either, then function
doesn't depend on any kconfig-dependent build-time state, and (given
that we use -ffunction-sections) it won't appear in output binaries
unless called.
And there are use cases (e.g. z_smp_start_cpu()) where we need that
function even when BOOT_DELAY is enabled.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The free run timer will be used to count before entering hibernate
mode. Move the related registers to the head file for accessing.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
We add disable event timer at the beginning of critical section
for two reason:
1.For K_TICKS_FOREVER case: since no future timer interrupts
are expected or required, so we disable the event timer.
2.Others case: according it81202 spec, when timer enable bit
from 0->1, the timer will reload counts and start countdown.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Instead of putting object files inside libzephyr.a,
simply build a separate static library as most other
driver types are doing this already.
Also sort the entries alphabetically.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add config macro to set interrupt as level triggered for ARM CPUs
Merge all timer configures into one place, then no need to overwrite
hpet_timer_conf_get/set() functions in SoC layer
Make hpet_timer_comparator_set() as the only register access function
to implemented in the SoC layer
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Instead of passing target states, use actions for device PM control.
Actions represent better the meaning of the callback argument.
Furthermore, they are more future proof as they can be suitable for
other PM actions that have no direct mapping to a state. If we compare
with Linux, we could have a multi-stage suspend/resume. Such scenario
would not have a good mapping when using target states.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Since the state is no longer modified by the device PM callback, just
use the state value.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
z_smp_init() is only available if CONFIG_SMP is defined,
smp_timer_init() also depends on two Kconfig parameters. Also make it
conditional in cavs_timer.c. Also clarify some SMP-related comments
there.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This converts register access from macro to functions.
This allows SoCs to override these functions if needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows the HPET timer to use kconfig to specify clock
frequency instead of relying on calculation at runtime.
When the frequency is known at build, this allow the toolchain
to optimize some calculations.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This renames MIN_DELAY to HPET_CMP_MIN_DELAY, and also allows it
to be overridden. The default delay is for HPET with relative
high frequency, and may not suitable for all HPET
implementations.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This extracts the hard-coded value into a macro which can be
overridden. This is in preparation for SoCs where the period
is not in femptoseconds.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
RTC interrupt was reading CC value and passing it to the handler.
However, higher priority interrupt could preempt RTC interrupt
and set new CC value. In that case CC value read in the RTC
interrupt context was not the one that triggered the interrupt.
Added fallback to COUNTER value if that case is detected.
Using COUNTER is not as precise as CC because it returns time
when event was handled and not when event occured but it is the
only option since CC value is overwritten.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add NXP Kinetis Low Power Timer (LPTMR) OS timer driver shim. Since the
LPTMR does not support asynchronous changes to the timer period, only
non-tickless mode is supported.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The callback is not used anymore, so just delete it from the pm_control
callback signature.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
For esp32c3 related ROM located functions instead
of esp32c3_rom.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Move all PM_DEVICE_STATE_* definitions to an enum. The
PM_DEVICE_STATE_SET and PM_DEVICE_STATE_GET definitions have been kept
out of the enum since they do not represent any state. However, their
name has not been changed since they will be removed soon.
All drivers and tests have been adjusted accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix for Issue#35658.
Update the custom vector table to add the OS Event timer
interrupt which is used on RT685 as the kernel system timer
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add the lptim1 device node definition and enable the corresponding
exti interrupt in sys_clock_driver_init().
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The stm32_lptim driver is hardcoded to use lptim1.
Make the Kconfig option depend on the presence of the node label in the
devicetree, so that there's one less list of supported SoC to keep track
of.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
In npcx series, we use ITIM64 as system kernel timer. Its source clock
frequency must equal to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This CL
added check during initialization to prevent ambiguous condition.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Make the APIC_TIMER_IRQ_PRIORITY Kconfig depend on APIC_TIMER ||
APIC_TSC_DEADLINE_TIMER to hide it in menuconfig when not applicable.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
As per description of the sys_clock_elapsed() function, "the kernel
will call this with appropriate locking, the driver needs only provide
an instantaneous answer". Remove then the unnecessary locking from the
function, as it only adds an undesirable delay.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Replace suffix ull to ULL to increase code readability and prevent
unexpected behaviours, because the lowercase character l shall not be
used in a literal suffix
Found as a coding guideline violation (MISRA R7.3) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
With this patch the sys_clock_set_timeout function counts the cycles
elapsed while computing the systick timer's new load (tickless mode).
This cycles are then added to the total cycle count instead of being
lost.
This patch mitigates uptime drifting in tickless mode (especially when
high frequency timers are registered).
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
-ENOSYS should be returned if the operation is not implemented. This
issue was causing some PM tests to fail, as -ENOSYS was expected.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The context parameter used across device power management is
actually the power state. Just use it and avoid a lot of
unnecessary casts.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt. Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic. The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default. Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").
Really this is just ideal for Zephyr. So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead. All modern hardware has
what it needs. The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Remove the config BOOT_TIME_MEASUREMENT and corresponding #ifdef'd code
throughout (kernel/init.c, idle.c, core/common.S , reset.S, ... ) which
hold the extern hooks for z_timestamp_main and z_timestamp_idle in the
removed boot_time test suite.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
During polling ITEN bit to make sure ITIM timer is enabled, we might
have the chance that npcx_itim_evt_enable() return fake error when
timeout expired but ITEN bit is set already if CONFIG_ZERO_LATENCY_IRQS
is enabled. (Since SVCall's interrupt priority is not the highest, the
other interrupts with IRQ_ZERO_LATENCY flag could preempt CPU resource
at this moment.)
In order to prevent return fake error code, this CL adjusts the check
conditions for ITEN bit and timeout.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
There was an inconsistency in the API as z_nrf_rtc_timer_chan_alloc
returned int but other function were using uint32_t for channel
argument. Updated api to use int32_t everywhere.
Update nrf_802154 driver which was using this api to use int32_t.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add initial support for the Cortex-M55 Core which is an implementation
of the Armv8.1-M mainline architecture and includes support for the
M‑profile Vector Extension (MVE).
The support is based on the Cortex-M33 support that already exists in
Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This feature predated the tickless kernel and has been in legacy mode
for a while. We now have no drivers or systems that do not support
tickless, so remove this option and cleanup the code to only use
tickless.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is another API that is being used in all timer drivers and is not
internal to the clock subsystem. Remove the leading z_ and make promote
it to a cross-subsystem API.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The clock/timer APIs are not application facing APIs, however, similar
to arch_ and a few other APIs they are available to implement drivers
and add support for new hardware and are documented and available to be
used outside of the clock/kernel subsystems.
Remove the leading z_ and provide them as clock_* APIs for someone
writing a new timer driver to use.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
If next_timeout() returns INT_MAX and pass it to
z_clock_set_timeout(), and machine goes to freeze or slow down.
Bad scenario as follows:
- If an argument int32_t ticks is set large value 0xffffffff,
ticks = MAX(MIN(ticks - 1, (int32_t)MAX_TICKS), 0);
replaces it into MAX_TICKS.
- uint32_t cyc will be set near by 0xffffffff
(this is 0xfffd7280 in 100 ticks per second).
- Add adjustment to cyc, adjustment max value is MAX_CYC.
(cyc = 0xffff14fd)
- Over 0x80000000 value of uint32_t is considered as negative
value of int32_t.
if ((int32_t)(cyc + last_count - now) < MIN_DELAY)
This condition is always true.
- Because cyc += CYC_PER_TICK will get overflow, driver sets mtimecmp
near value of current mtime.
(cyc = 0x00007fc0)
- Next timer interrupt will happen soon after return from interrupt
handler.
- By repeating these events, machine cannot go to next instruction,
and it's going to freeze or slow down.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Use timeout mechanism instead of unbounded loop during enabling ITIM32
module which source clock is LFCLK (32KHz).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Qemu when running more than one processor has a known synchronization
bug where counter values read from the HPET (notionally a single
global device) can be seen going "backwards" when read from different
CPUs.
There was a pre-existing workaround in the ISR that knew about this,
but the problem can crop up anywhere the counter value is used. In
particular I caught it aliasing with the "max_ticks" computation in
z_clock_set_timeout(), where it would cause a rollover and the
resulting negative comparator value would result in no end of
hilarity.
Wrap all access to the counter register with a counter() inline that
(when the workaround is enabled) forces the result to be monotonic by
clamping it to a minimum of one more than the previously read value.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This include make possible to use the arm_arch_timer on
platform such as Cortex-A9 or Cortex-R7 which has support for
ARM Global Timer.
The global timer is a 64 bit incrementing counter, memory-mapped
in the private memory region.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The count register is 64 bits, but we're a 32 bit CPU that can only
read four bytes at a time, so a bit of care is needed to prevent
racing against a wraparound of the low word. Wrap the low read
between two reads of the high word and make sure it didn't change.
Fixes#31599
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
idle is only considered in other timer implementations if ticks ==
K_TICKS_FOREVER but in arm_arch_timer. Just fix it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
TICKLESS_CAPABLE is now selectable only and without prompt, so remove it
from _defconfig files and select it directly by the timer.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
z_timer_idle_enter is declared only when CONFIG_TICKLESS_IDLE is
selected. This function is not implemented anywhere, but the only
driver including this header is not TICKLESS_CAPABLE. So, no undefined
reference will happen.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Due to clock discrepancy, busy waiting for 15us was not covering for
half tick in certain cases. Busy wait runs from HF clock source.
Increased to 19us to cover it. Anyway, this case is hit very rarely,
only when there was aborted, not-cancelled compare value that was
about to expire. Because of that, increase shall not impact the
performance.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
For a while now, we've had two APIC drivers. The older was preserved
initially as the new (much smaller, "new style") code didn't have
support for Quark interrupt handling. But that's long dead now. Just
remove it.
Note that this migrates the one board using this driver (acrn) to
CONFIG_APIC_TIMER instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As timer interrupt is level triggered, we need to mask it before leaving
ISR or it will be delivered again.
Also, Xen automatically masks timer interrupt when it injects IRQ to
a guest, so we need to unmask it again, when setting new timeout.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is about the it8xxx2 timer driver.
We use the timer 5 as system timer for count time,
so the timer interrupt is trigged by it.
Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
Add a new test for k_busy_wait and cpu_hold
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Wolfgang Puffitsch <wopu@demant.com>
In native_posix and nrf52_bsim add the cpu_hold() function,
which can be used to emulate the time it takes for code
to execute.
It is very similar to arch_busy_wait(), but while
arch_busy_wait() returns when the requested time has passed,
cpu_hold() ensures that the time passes in the callers
context independently of how much time may pass in some
other context.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
When tickless mode was disable, sys clock timeout handler was calling
public API function for setting new compare value. Public API function
asserts when chan 0 is used which is reserved for system clock.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Added clearing of CC event which may occure due to previous
CC value which was closed to current counter value.
Fixed int_mask initialization.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Fix TIMER0 and RTC0 being selectable when using out-of-tree Bluetooth
controller.
Generalize the Kconfig to have the features that use the HW peripheral
select them as reserved to make the dependencies more manageable.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
