z_nxp_os_timer_ignore_timer_wakeup() was only added
when Standby mode was enabled. Move this function
out of the conditional section.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
We can both optimize and clean up the code by using short circuit logic
and static variables instead of stack variables.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Refactor ISR by:
1) making a helper function to put the tickful calculation in, to reduce
an indentation level and cognitively separate this case while reading
2) Rewrite the calculations to simplify them. More info on that below.
Math changes:
- In the ISR, there was a variable called "now" which represented the
current cycle count of the timer. last_count was updated using a
calculation based on the number of elapsed ticks
and the hardware cycles per second value. However, this is
redundant because mathematically, this is equivalent to "now". So the
variable can just be set to now.
Proof is that the previous calculation was (in programming language):
(1) last_count = last_count + elapsed_ticks * CYC_PER_TICK
So let's rewrite this as the following to be clear about the different
values we are talking about here (in math language):
(2) count[t] = count[t-1] + elapsed_ticks * CYC_PER_TICK
We calculated elapsed ticks in the function as:
(3) elapsed_ticks = (now - last_count) / CYC_PER_TICK
(4) elapsed_ticks = (now - count[t-1]) / CYC_PER_TICK
Rearranging (2), we see
(5) elapsed_ticks = ( count[t] - count[t-1] ) / CYC_PER_TICK
Substituting this into (4), we get:
(6) ( count[t] - count[t-1] ) / CYC_PER_TICK =
(now - count[t-1]) / CYC_PER_TICK
Doing simple algebra, you can see we result with:
(7) count[t] = now
So therefore, we can simplify the programming expression to
(8) last_count = now
- The other change is regarding the calculation of the next tick match
value for tickful kernel mode. The previous calculation was doing:
(1) next = now + CYC_PER_TICK
We know that last_count is equivalent to now, at this point in the code
with the first change:
(2) next = last_count + CYC_PER_TICK
And then, for some reason, we are adding yet another CYC_PER_TICK to
next if (next - now) < MIN_DELAY. The reason for that I do not
understand, but let's write that down:
(3) next - now < MIN_DELAY
Now rewrite (2) as (4) and (3) as (5):
(4) count[t+1] = count[t] + CYC_PER_TICK
(5) count[t+1] - count[t] < MIN_DELAY
And now we substitute (4) into (5):
(6) count[t] + CYC_PER_TICK - count[t] < MIN_DELAY
And simplify:
(7) CYC_PER_TICK < MIN_DELAY
So actually no runtime calculations are needed here, this is a
hardcoding. The reason for this calculation I don't know, but we can
simplify the code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There are a couple places where effectively the exact same calculation
is done. Refactor to share code to do this calculation to make it easier
to read, and explode the code to multiple statements to be even easier
to follow the calculation. Compiler will likely optimize the same way
when opt enabled. Rename dticks variable to be more explicit what that
means (elapsed ticks).
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Refactor to remove nesting and consolidate lines of code.
I also ran clang format but that actually did not change very much in
addition to what I had already changed manually.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The counter that is used in Power Mode 3 to track System time could
overflow for large timeouts.
Add an API that the power system could use to ignore wakeup events
from the timer.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Use channel 0 for RTC wrapping. Skip that channel when processing
channels.
Fix algorithm that prevents setting CC=0 when custom wrapping is used.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Allowed use of counter bit width lower than hardware 24.
In that case, PPI connection is established to trigger
clear task once maximum value is reached.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Fixed build fail since 4c93fcd35b.
Fixed test run fail on Ambiq platforms.
Added Ambiq section in the test.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
when CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC set to 960M
and CONFIG_SYS_CLOCK_TICKS_PER_SEC set to 100
the MAX_TICKS will be zero or even negative value, which is not
expected.
so need add a protection here downgrading the accuracy to
its as high as possible
also add build message to show that tickless has no effect
fixes: #36766
there used to be a workaround, not a fix,
either change the CONFIG_SYS_CLOCK_TICKS_PER_SEC=200
or
CONFIG_PM to set the CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
to 32678
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Turn MCX series into families.
Reasoning:
1. The MCX SOCs are quite different from each other and having them all
under one family in the HWMv2 hierarchy is fruitless because there
are so many differences that it is confusing to try to introduce
family-level code and configs since they would each only apply to a
subset of the series. There is almost nothing that can be shared
between all of them. Which is why there are comments in the MCX
family files saying not to put anything in them. This is a technical
waste.
2. Therefore, turning all of them into families is almost 0 effort and
makes sense. It will allow these different types of MCX to be
further subdivided into series in the future as the MCX portfolio
expands and such division will be necessary as new SOCs within each
letter family are released.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
To be consistent with the definition of label stm32_lp_tick_source,
be sure "st,timeout" is taken from the LPTIM defined as lp_tick_source.
Then, fix the computation of lptim_time_base.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Makes the choice CORTEX_M_SYSTICK_LPM dependent upon the
CORTEX_M_SYSTICK to prevent its default from showing up in
the .config of projects that do not use the CORTEX_M_SYSTICK
timer driver.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
The GRTC counter is not cleared at startup, therefore the
`last_count` variable needs to be initialized accordingly.
This change:
- Prevents overflow of the `sys_clock_announce()` int32_t parameter
- Ensures the correct uptime value, which should be reset during
initialization
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
The original logic relied on the tick passed in. This method
is inaccurate as the tick value passed in was the exit latency.
Update the code to calculate the remaining time left and set
a counter using this value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. add the ostimer
2. by default, the systick is used.
3. The ostimer could be tested with below configure in xxx.overlay:
&systick {
status = "disabled";
};
&ostimer0 {
status = "okay";
};
And below configure in xxx.conf:
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Selects TIMER_HAS_64BIT_CYCLE_COUNTER as an dependency for MCUX_OS_TIMER
This already is supported in the timer implementation in
drivers/timer/mcux_os_timer.c
Signed-off-by: Tomas Groth Christensen <tgc@foss.dk>
Converting absolute system ticks to RTC ticks is simple. It needs to be
multiplied by CYC_PER_TICK (which by default is 1). Complex algorithm
was used when driver was not tracking current 64 bit tick and function
was returning uint32_t.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The EC timer runs at 9.2 MHz, which leads to a non-integer number of
ticks per microsecond. This causes slight overestimation when delays
are computed using whole ticks (e.g., using 10 ticks for 1 µs).
To address this, the busy wait calculation is adjusted with a
compensation factor to minimize cumulative timing error over time.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Timer 7 is not used in timer driver, which means that timer
driver doesn't initialize timer 7, it's just declared in dtsi.
So I remove it, timer 7 will be used as alarm timer for counter driver.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This driver currently only supports one instance of this timer and uses
it as the system clock. The instance is selected by being the first one
listed in DT in all places except sys_clock_driver_init() where it uses
the node label "systick_timer".
This driver should be fixed to correctly support multiple instances
of this timer, and the one used for the system timer should be selected
based on a flag or alias, not based on label.
For now simply use the 0th instance like everywhere else which removes
the need to have this node labeled a special way and makes no functional
changes to current users.
Signed-off-by: Andrew Davis <afd@ti.com>
This commit updates the riscv_machine_timer driver to resolve MTIME and
MTIMECMP register addresses by their `reg-names` instead of relying on
index order.
This improves clarity and robustness in DTS bindings, and is a prerequisite
for handling cases where not both MTIME and MTIMECMP registers are present
or accessible.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Expand the current systick compatibility to include the CH32V00x
series. Change the HAL compatibility to include all of the CH32V
family.
Signed-off-by: Michael Hope <michaelh@juju.nz>
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
for high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.
Signed-off-by: Michael Hope <michaelh@juju.nz>
This patch allows ti_dmtimer to provide the symbol z_sys_timer_irq_for_test
whenever tests are enabled. Not providing this results in failing some
kernel test cases which require this symbol.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
