This reverts commit 67a29d7f98.
After this commit a BT testcase
tests/bsim/bluetooth/ll/throughput/tests_scripts/\
gatt_write_no_phy_update.sh
started failing, where the RTC1 interrupt fires
in an infinite loop after 4m:17s.
This is blocking all BT related PRs.
Let's revert this commit while the issue is debugged to unblock
development.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
sys_clock_set_timeout() computed the compare value as
cyc = ticks * CYC_PER_TICK + unannounced;
cyc = DIV_ROUND_UP(cyc, CYC_PER_TICK) * CYC_PER_TICK;
target = last_count + cyc;
The DIV_ROUND_UP forces the fire onto the next tick boundary *after*
the requested point, but the driver never subtracts the unannounced
sub-tick offset back out. When the caller arms partway through a tick
(the common case), the timer therefore fires one tick later than the
kernel asked for -- k_timer_start(K_TICKS(N), ...) ends up firing at
roughly N+2 ticks instead of N+1. This is what GoranWall observed on
nrf52840dk: the new tests/kernel/timer/timer_behavior ramp test fails
on specific delay values.
Compute the target directly as
target = last_count + (last_elapsed + ticks) * CYC_PER_TICK
where last_elapsed is the tick count the kernel last observed via
sys_clock_elapsed(), and last_count is tick-aligned by construction.
The fire lands at exactly (last_elapsed + ticks) ticks past the last
announce, regardless of when within a tick the caller armed.
Track last_elapsed in sys_clock_elapsed() and reset it in
sys_clock_timeout_handler() at announce. The COUNTER_HALF_SPAN
wrap-protection check is preserved. Clamp on ticks alone since the
24-bit compare register limit is relative to the current counter,
and target - now = ticks * CYC_PER_TICK - sub_tick.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Some MCUX LPTMR instances expose counters narrower than 32 bits.
Raw uint32_t subtraction in tickless mode can treat a 16-bit
hardware wrap as a 32-bit wrap.
Compute elapsed time and compare distances in the hardware counter
domain with COUNTER_MAX.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Previously announced_cycles was set directly to the current counter
value, which includes sub-tick remainder cycles from ISR latency.
Over time these remainders accumulate, causing the announced tick
boundary to drift away from the true tick grid.
Advance announced_cycles in whole-tick increments instead, so that
the sub-tick fraction is naturally absorbed by the next interval
rather than compounding across interrupts.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add Kconfig options to control whether the GRTC timer is stopped
and/or cleared when the driver is uninitialized (e.g. when
sys_clock_disable() is called).
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Selecting MCUX_LPTMR_TIMER directly from
/chosen/zephyr,system-timer broadens the default behavior for
any SoC DTSI that now sets the chosen node. KE1xF only
intends to use LPTMR under PM, while MCX-W7xx and i.MX95 M7
still require their SoC-specific selection rules.
Keep the generic Kconfig selection policy implicit and retain
the SoC-specific enablement rules in the MCX-W7xx and i.MX95
M7 defconfigs.
This keeps the chosen-based instance selection while avoiding
unintended system timer changes outside the narrow fix scope.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The custom arm_arch_timer arch_busy_wait() computed the wait duration as:
cycles_to_wait = sys_clock_hw_cycles_per_sec() / USEC_PER_SEC *
(uint64_t)usec_to_wait;
Integer division applied first. When the timer frequency is not an
integer multiple of USEC_PER_SEC (e.g. 62.5 MHz on Cortex-A53), the
fractional cycles-per-microsecond are silently dropped, making every
call to k_busy_wait() return short by up to 0.8% of the requested
duration -- breaking the API contract that busy_wait() is guaranteed
to wait at least the requested number of microseconds.
Replace the open-coded conversion with k_us_to_cyc_ceil64(), which
multiplies first and rounds up, so the resulting cycle count always
covers at least the requested microseconds.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Introduce CONFIG_RISCV_S_MODE to select Supervisor-mode execution.
Add depends on !RISCV_S_MODE to RISCV_PMP since PMP CSRs are
inaccessible from S-mode.
Add an M-mode SBI shim (reset.S + sbi.S) that configures exception
delegation, PMP, and counter access before dropping to S-mode via mret.
The shim handles SBI_SET_TIMER ecalls from S-mode and forwards MTIP to
STIP so the supervisor timer driver works without a full SBI firmware.
Introduce privilege-level abstractions in isr.S (RV_CAUSE, RV_EPC,
RV_STATUS, RV_TVAL, etc.) and update all runtime code that previously
accessed M-mode-only CSRs (mcause, mtval, mstatus, mie, mip) to use the
S-mode equivalents when CONFIG_RISCV_S_MODE is set.
ARCH_EXCEPT in kernel context uses ebreak (cause=3, Breakpoint) instead
of a direct z_riscv_fatal_error() call. In S-mode, ecall (cause=9) is
kept in M-mode for SBI and never reaches the S-mode exception handler;
a direct call with NULL esf caused the stack unwinder to crash into an
infinite fault loop. ebreak is delegated to S-mode by our medeleg
configuration; isr.S treats ebreak with t0=RV_ECALL_RUNTIME_EXCEPT the
same way M-mode treats ecall-based ARCH_EXCEPT.
Signed-off-by: Alexios Lyrakis <alexios.lyrakis@gmail.com>
Add sys_clock_is_locked(), the analog of z_spin_is_locked() for the
timer lock exposed via sys_clock_lock(). Use it to assert lock
ownership in sys_clock_set_timeout() and sys_clock_elapsed() of the
six timer drivers that were migrated to sys_clock_lock() and
consequently no longer acquire anything internally in those callbacks
(arm_arch_timer, riscv_machine_timer, xtensa_sys_timer, hpet,
apic_tsc, intel_adsp_timer).
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
For next-generation it51xxx series, external timers switch
from count-up to count-down when combination mode is enabled.
This change introduces Kconfig option to allow selecting
count-up mode according to hardware design.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add support for configuring the LPTMR as a wakeup source by integrating
with the WUC (Wakeup Controller) subsystem.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Use the WFET (Wait For Event with Timeout) instruction, introduced in
Armv8.8-A (FEAT_WFxT), to let the CPU enter a low-power state during
arch_busy_wait() instead of spinning on the counter.
The availability of WFxT is detected at runtime by reading
ID_AA64ISAR2_EL1. When the feature is absent, the existing polling
loop is used as before.
Also fix the cycles_to_wait computation to use 64-bit multiplication
to avoid truncation with large usec_to_wait values.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
IDLE exit is programmed to happen shortly before systimer
programmed wake-up event happens. If the interrupt from
the timer happens before, idle_exit() does not run, as
timeout_idle flag is cleared at the ISR. Fix condition for
both systimer (ESP32) and xtensa drivers.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Migrate intel_adsp_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate apic_tsc to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate hpet to the unified timer lock API. Replace the driver-private
spinlock with sys_clock_lock()/sys_clock_announce_locked().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate xtensa_sys_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked()
so that the hardware cycle baseline and the kernel tick counter are
always updated under the same lock.
Also migrate sys_clock_idle_exit() which updates driver state and
announces ticks on LPM exit.
Add extern declarations for sys_clock_cycle_get_32/64 in
arch/xtensa/arch.h, consistent with all other architectures, to
avoid a circular include dependency with system_timer.h. Xtensa
was the only architecture missing them.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate riscv_machine_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked()
so that the hardware cycle baseline (last_count) and the kernel tick
counter (curr_tick) are always updated under the same lock.
This eliminates a race on SMP where sys_clock_elapsed() could observe
the updated last_count before sys_clock_announce() had advanced
curr_tick, causing time-dependent kernel operations to see inconsistent
values.
Remove internal locking from sys_clock_set_timeout() and
sys_clock_elapsed() as they are now always called with the timer lock
held.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate arm_arch_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked()
so that the hardware cycle baseline (last_cycle) and the kernel tick
counter (curr_tick) are always updated under the same lock.
This eliminates a race on SMP where sys_clock_elapsed() could observe
the updated last_cycle before sys_clock_announce() had advanced
curr_tick, causing time-dependent kernel operations to see inconsistent
values.
Remove internal locking from sys_clock_set_timeout() and
sys_clock_elapsed() as they are now always called with the timer lock
held.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Replace SOC_SERIES_CH32V00X with SOC_SERIES_QINGKE_V2C to maintain
consistent naming across SOC series.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
The OpenRISC 1000 Tick Timer is tightly coupled to the or1k CPU core, and
is explicitly designed to facilitate task scheduling and high-resolution
timing.
The timer is documented in Chapter 14 of the OpenRISC 1000 Architecture
Manual:
https://openrisc.io/or1k.html#__RefHeading__504849_595890882
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
1. Keep drivers/timer/cortex_m_systick.h as a compatibility
shim for legacy Cortex-M-specific names.
2. Switch to use the generic low-power companion timer API
for the Cortex-M SysTick driver.
3. Mark the global CORTEX_M_SYSTICK_LPM_* kconfig options
as 'DEPRECATED' and replace them with SYSTEM_TIMER_LPM_*
4. Rename 'zephyr,cortex-m-idle-timer' to
'zephyr,system-timer-companion'
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Introduce a system timer driver that uses the MAX32 Wake-up Timer as the
system tick source. This enables the MAX32 SoC family to use the WUT for
kernel timing operations.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Replace the single-instance assumption with a zephyr,system-timer chosen
node approach. The timer driver reads its hardware instance directly from
DT_CHOSEN(zephyr_system_timer) instead of assuming instance 0. The
counter driver skips whichever instance is designated as the system timer,
allowing both drivers to coexist on SoCs with multiple LPTMR instances.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Don't allow the LPTIM system clock driver to be enabled if the required
nodelabel `stm32_lp_tick_source` does not exist. This prevents incorrect
usage which could result in non-trivial build failures.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add support for hardware-generated periodic compare events using
the GRTC interval feature. Once configured, the hardware generates
compare events at a fixed interval without CPU intervention.
The feature is available only on channels defined as
"extended-channels" in the devicetree.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Add systimer compensation for time spent in light sleep while stalled.
Add sys_clock_idle_exit() for dticks announcement when leaving
light sleep.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add CCOUNT compensation for time spent in LPM mode (CPU stalled).
Add sys_clock_idle_exit() for dticks announcement when leaving LPM.
Add hooks for SoC specific implementation of LP timer timestamp call.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
When tickless is enabled, it is necessary to ensure
that lptmr can be set for a period of time instead of generating
an interrupt at one tick.
LPTMR hardware does not synchronize writes to the
compare register (CMR)
If CMR is changed exactly when the counter increments,
the hardware may compare part of the counter against
the old CMR value and part against the new one, leading to TCF
being set incorrectly on some SoCs.
Reorder the update sequence to:
- disable the LPTMR interrupt,
- clear TCF,
- write the new CMR,
- re-enable the interrupt.
This provides a safe workaround for tickless mode case.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Add support for prescaler bypass configuration via devicetree
property. This aligns the timer driver with the counter driver
implementation.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The nrf54l soc init configures power and clock properties like
applying trims, capacitance and setting up regulators. This must
precede the grtc driver initializing the sys clock, as it depends
on these clocks being initialized on the nrf54l series socs.
Update the nrf54l soc init to be EARLY 0, and set grtc sys clock
driver init to EARLY 1. Additionally add comments explaining why
these specific init levels where chosen.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Implement z_sys_clock_hw_cycles_per_sec_update() for the Cortex-M
SysTick driver to support runtime system timer frequency changes
when CONFIG_SYSTEM_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_UPDATE is enabled.
Also extend the conditional compilation guard for the external
z_clock_hw_cycles_per_sec declaration to include the runtime update
configuration option.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add infrastructure to support updating the system timer frequency at
runtime on platforms where the timer clock rate can change dynamically.
Introduce CONFIG_SYSTEM_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_UPDATE Kconfig
option that enables runtime frequency updates. This option is mutually
exclusive with CPU_FREQ_PER_CPU_SCALING since the system timer frequency
is tracked as a single global value.
Add z_sys_clock_hw_cycles_per_sec_update() API that platforms must call
after applying a system timer clock change. The kernel provides a weak
default implementation that updates the stored frequency value used by
sys_clock_hw_cycles_per_sec().
System timer drivers that cache derived constants or need to reprogram
hardware on frequency changes can provide a strong override of this
function to maintain driver state consistency while ensuring the stored
frequency is also updated.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The RV32 core does not implement RISC-V mtime, so add a new system
timer driver uses a peripheral timer for this functionality.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
In tickless mode, advance last_count in whole tick increments rather
than setting it to the raw timer value. This prevents sub-tick ISR
latency from accumulating in last_count, which would otherwise manifest
as long-term timer drift.
The fix inverts the conditional logic so that:
- Tickless mode: last_count += elapsed_ticks * CYC_PER_TICK
- Tickful mode: last_count = now (unchanged behavior)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Prevents building the driver entirely if the PM symbol is selected instead
of erroring out via a compiler pragma.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Zephyr was crashing in hpet when the base address
wasn't set yet when using MMU and when
`cyc_per_tick` was not defined yet.
Signed-off-by: Juliusz Sosinowicz <juliusz@wolfssl.com>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Due to the hardware limitation, the time between the CPU wake-up IRQ fire
(IRQ 23) and the next call of LL_RADIO_TIMER_SetCPUWakeupTime should not
be less than 16 MTU (Machine Time Unit), i.e. approximately 30us.
otherwise, the next CPU wake-up doesn't happen unless the timer wraps.
Lock IRQs while sys_clock_set_timeout is being executed.
Remove HAL_RADIO_TIMER_WakeUpCallback and it will be implemented
differently in the future.
Remove HAL_RADIO_TIMER_TimeoutCallback as it is not needed anymore.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Moving the reset of ltpim hw ip at the beginning of
sys_clock_driver_init to improve the reliability of lptim hw
configuration sequence.
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
