drivers: timer: Refactor x86 system timer selection

Refactor timer selection to allow to select only one timer.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>

boards/x86/up_squared/Kconfig.defconfig

@@ -15,9 +15,6 @@ config HEAP_MEM_POOL_SIZE
 config BUILD_OUTPUT_STRIPPED
 	default y
 
-config APIC_TSC_DEADLINE_TIMER
-	default y
-
 # TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 1593600000 if APIC_TSC_DEADLINE_TIMER

drivers/timer/Kconfig

@@ -65,7 +65,7 @@ config SYSTEM_CLOCK_LOCK_FREE_COUNT
 
 source "drivers/timer/Kconfig.altera_avalon"
 source "drivers/timer/Kconfig.ambiq"
-source "drivers/timer/Kconfig.apic"
+source "drivers/timer/Kconfig.x86"
 source "drivers/timer/Kconfig.arcv2"
 source "drivers/timer/Kconfig.arm_arch"
 source "drivers/timer/Kconfig.cavs"
@@ -73,7 +73,6 @@ source "drivers/timer/Kconfig.cc13xx_cc26xx_rtc"
 source "drivers/timer/Kconfig.cortex_m_systick"
 source "drivers/timer/Kconfig.esp32c3_sys"
 source "drivers/timer/Kconfig.gecko"
-source "drivers/timer/Kconfig.hpet"
 source "drivers/timer/Kconfig.ite_it8xxx2"
 source "drivers/timer/Kconfig.leon_gptimer"
 source "drivers/timer/Kconfig.litex"

drivers/timer/Kconfig.hpet

@@ -1,17 +0,0 @@
-# Copyright (c) 2014-2015 Wind River Systems, Inc.
-# Copyright (c) 2016 Cadence Design Systems, Inc.
-# Copyright (c) 2019 Intel Corp.
-# SPDX-License-Identifier: Apache-2.0
-
-config HPET_TIMER
-	bool "HPET timer"
-	default y
-	depends on DT_HAS_INTEL_HPET_ENABLED
-	select IOAPIC if X86
-	select LOAPIC if X86
-	imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
-	select TICKLESS_CAPABLE
-	select TIMER_HAS_64BIT_CYCLE_COUNTER
-	help
-	  This option selects High Precision Event Timer (HPET) as a
-	  system timer.

drivers/timer/Kconfig.x86

@@ -1,12 +1,30 @@
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2016 Cadence Design Systems, Inc.
-# Copyright (c) 2019 Intel Corp.
+# Copyright (c) 2019-2023 Intel Corp.
 # SPDX-License-Identifier: Apache-2.0
 
-menuconfig APIC_TIMER
-	bool "New local APIC timer"
+choice
+	prompt "Default System Timer"
+	default HPET
 	depends on X86
-	depends on LOAPIC
+	help
+	  Select Default System Timer.
+
+config HPET_TIMER
+	bool "HPET timer"
+	depends on DT_HAS_INTEL_HPET_ENABLED
+	select IOAPIC
+	select LOAPIC
+	imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
+	select TICKLESS_CAPABLE
+	select TIMER_HAS_64BIT_CYCLE_COUNTER
+	help
+	  This option selects High Precision Event Timer (HPET) as a
+	  system timer.
+
+config APIC_TIMER
+	bool "Local APIC timer"
+	select LOAPIC
 	select TICKLESS_CAPABLE
 	select SYSTEM_CLOCK_LOCK_FREE_COUNT
 	help
@@ -16,6 +34,24 @@ menuconfig APIC_TIMER
 	  without complete APIC emulation).  Modern hardware will work
 	  better with CONFIG_APIC_TSC_DEADLINE_TIMER.
 
+config APIC_TSC_DEADLINE_TIMER
+	bool "Local APIC timer using TSC deadline mode"
+	select LOAPIC
+	select TICKLESS_CAPABLE
+	select TIMER_HAS_64BIT_CYCLE_COUNTER
+	help
+	  Extremely simple timer driver based the local APIC TSC
+	  deadline capability.  The use of a free-running 64 bit
+	  counter with comparator eliminates almost all edge cases
+	  from the handling, and the near-instruction-cycle resolution
+	  permits effectively unlimited precision where needed (the
+	  limit becomes the CPU time taken to execute the timing
+	  logic). SMP-safe and very fast, this should be the obvious
+	  choice for any x86 device with invariant TSC and TSC
+	  deadline capability.
+
+endchoice
+
 if APIC_TIMER
 
 config APIC_TIMER_IRQ
@@ -52,23 +88,6 @@ endif # APIC_TIMER_TSC
 
 endif # APIC_TIMER
 
-config APIC_TSC_DEADLINE_TIMER
-	bool "Even newer APIC timer using TSC deadline mode"
-	depends on X86
-	select LOAPIC
-	select TICKLESS_CAPABLE
-	select TIMER_HAS_64BIT_CYCLE_COUNTER
-	help
-	  Extremely simple timer driver based the local APIC TSC
-	  deadline capability.  The use of a free-running 64 bit
-	  counter with comparator eliminates almost all edge cases
-	  from the handling, and the near-instruction-cycle resolution
-	  permits effectively unlimited precision where needed (the
-	  limit becomes the CPU time taken to execute the timing
-	  logic). SMP-safe and very fast, this should be the obvious
-	  choice for any x86 device with invariant TSC and TSC
-	  deadline capability.
-
 config APIC_TIMER_IRQ_PRIORITY
 	int "Local APIC timer interrupt priority"
 	depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER