For drivers that support CONFIG_DEVICE_POWER_MANAGEMENT there are some
cases that look like:
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
DEVICE_DEFINE()
#else
DEVICE_AND_API_INIT()
#endif
There is no need to special case this as the pm_control_fn argument to
DEVICE_DEFINE will just be ignored in the
!CONFIG_DEVICE_POWER_MANAGEMENT case. So we can cleanup the code a
little and remove the #else cases for the drivers that do this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replaces all existing variants of value clamping with the MIN and MAX
macros with the CLAMP macro.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
This removes a semaphore unlock in init_spi function
which causes risks of competitive access
Signed-off-by: Clotilde Sattler <clotilde.sattler@stimio.fr>
Set stm32_dt_pinctrl_configure function as the unique entry point
to STM32 DT pinctrl management.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move pinctrl remap functions out of stm32f1 definition in order
to get it available to all series.
Allows use of more IS_ENABLED macros in calling drivers and make
code more readable.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Moved enabling SPI peripheral in front of the buffers loop.
Removed SPI DMA switching on in front of the buffers loop.
Signed-off-by: Łukasz Mazur <lukasz.mazur@hidglobal.com>
Removed SPI peripheral disabling when switching DMA to another buffer.
When using hardware chip select this would cause to stop driving
CS pin when swhitching buffers. This is different (and wrong) than
when used software CS.
Fixes#28833
Signed-off-by: Łukasz Mazur <lukasz.mazur@hidglobal.com>
Add an emulation controller which routes SPI traffic to an attached
emulator. Only one emulator is supported per bus at present, since
chip-selction functionality is not present.
This allows drivers for SPI peripherals to be tested on systems that
don't have that peripheral attached, with the emulator handling the SPI
traffic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Function spi_context_longest_current_buf() has been introduced in
commit ddef35c1da for the purpose of
getting the longest possible (potentially partial) SPI transfer
for which all currently active directions have a continuous buffer.
Such transfer can be done with taking advantage of a DMA that cannot
use scattered buffers (and this is the case for nRF SPI drivers with
which this function has been introduced).
Unfortunately, because of its inadequate name, later on this function
has been incorrectly used in other SPI drivers for getting the longer
of TX/RX buffers. And commit afc480f12b
recently "fixed" the implementation of this function, assumably to
adjust it to those incorrect uses, but this way it has also broken
the nRF SPI drivers.
Instead of restoring the original implementation of the function in
question, this commit adds a new one with functionality equivalent
to that original but with a hopefully less misleading name, and this
function is used in the nRF SPI drivers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enable by default the use of RAM buffers in the spi_nrfx_spim.c
driver for copying TX data located in flash (as SPIM peripherals
cannot transfer directly form flash). Without this patch, users can
get confused, especially when SPI transaction is used by an upper
level driver which does not check all error codes.
For size of the buffer, use the value used so far in the reel_board
default configuration and in the SPI loopback test, i.e. 8 bytes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Fix GPIO CS timing when using DMA. When using GPIO CS the
CS select was enabled after the DMA started the transfer,
resulting in the first few bits being transfered while
CS was still disabled.
- Fix TX or RX only DMA transfers. When only a RX or only
a TX transfer was requested the DMA never finished.
For the RX only cause the size on the transfer was
calculated by taking the TX buffer length (0), this
caused problems.
For the TX only transfer the RX buffer was set to NULL,
this caused the DMA to acctually writing data to the
adress 0x00000000. By using the dummy destination buffer
it now only writes to valid memory.
- Add semaphore to signal that DMA is ready, instead of
just busy waiting.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
These are all the case that coccinelle cannot find as they are inside
macro declarations.
Fixed via:
git grep -rlz -E "\(struct device \*" |
xargs -0 sed -i 's/(struct device/(const struct device/g'
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Some needed to wrap the device pointer into device's data, where others
needed only device's data to be passed to HAL callback function.
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add SPI driver for the Xilinx AXI Quad SPI IP. Despite the name, this IP
block supports both single, dual, and quad line widths.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Using SPIM_FREQUENCY_FREQUENCY_M32 to check if the device has HS-SPI and
able to use higher SPI clock than 8MHz.
Signed-off-by: Jui-Chou Chung <jui-chou.chung@nordicsemi.no>
Flexcomm's SPI SSEL (or CS) will be held until frame end.
FIFOWR[EOT] (kSPI_FrameAssert enum) is the register not set.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
To keep the bus fully loaded, the SAM0 has a fast path that recognises
special cases like TX only, RX only, or TX/RX of the same size.
Commit #ea2431f32f accidentally disabled this.
This increases the utilisation from around 30 % to around 90 % at 48
MHz.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 has a data register and a shift register. Data that is
written to the data register is transferred to the shift register by
the peripheral.
On the SAMD51, the CPU is fast enough that the first data write hasn't
been transferred to the shift register by the time the next data write
occurs, causing the second write to be dropped, causing the receiver
to wait forever.
Fix by spinning until the data register is empty.
Signed-off-by: Michael Hope <mlhx@google.com>
Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add an additional option to the spi_cs_control struct that records how
the pin has been configured in devicetree. For drivers that are not
updated, the CS behaviour is the same as before (Push-Pull).
Use the devicetree knowledge with the GPIO subsystem so that the correct
physical pin levels for the CS pin are automatically selected.
Fixes#26267
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Initialize the dummy data transfer so spi transfer is defined even for
an undefined tx data buffer. This aligns the rv32m1 spi driver with the
mcux spi driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
The consequent and alternate expressions for COND_CODE_1 must be
enclosed in parentheses, like this:
COND_CODE_1(PREDICATE, (consequent), (alternate))
The parens are missing in exactly one place in the tree. Fix it.
Reported-by: Peter Bigot <peter.bigot@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The power configuration is dependent on which SPI is physically used.
In order to allow DT_INST_FOREACH_STATUS_OKAY() to iterate through
instances without the assumption that index 0 corresponds to SPI0
(which would be incorrect in the case when only SPI1 is enabled),
we need to check the base address to identify which SPI is being dealt
with.
Fixes#25673
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Current dma struture code didn't allowed only rx channel removal,
disabling tx channel (in spi client node) was leading compilation
issue.
Fix this by moving conditional code inside SPI_DMA_CHANNEL macro and
get the part of code which is present or removed (SPI_DMA_CHANNEL_INIT)
outside of {}.
Additionally, fix indentation on '\' in whole instance init macros
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
With this change, the spi transceive with dma function
waits for the spi busy flag reset and for the dma transfer end.
Then it reloads the channels until all buffers are consumed.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This change avoids the reload of the dma channel
in the callback function, just sets the corresponding Tx, Rx flag.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Remove semicolon between instance invocations of DT_FOREACH_IMPL_ and
thus DT_INST_FOREACH. This provides more flexibility to the user. This
requires we fixup in tree users to add semicolon where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Attached Flexcomm SPI driver to the main clock used by the core.
This means setting the SPI clock the same value as the core clock.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name. We make
the assumption in the drivers that there is a single DMA controller
instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Clean up as we wish to move away from using these Kconfig settings.
Also removing them from the boards' default config.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Make drivers multi-instance wherever possible using DT_INST_FOREACH.
This allows removing DT_HAS_DRV_INST in favor of making drivers just
do the right thing regardless of how many instances there are.
There are a few exceptions:
- SoC drivers which use CMake input files (like i2c_dw.c) or otherwise
would require more time to convert than I have at the moment. For the
sake of expediency, just inline the DT_HAS_DRV_INST expansion for
now in these cases.
- SoC drivers which are explicitly single-instance (like the nRF SAADC
driver). Again for the sake of expediency, drop a BUILD_ASSERT in
those cases to make sure the assumption that all supported SoCs have
at most one available instance is valid, failing fast otherwise.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear. As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The optimisation in `spi_sam0_fast_txrx()` is broken, loading
two bytes into the `DATA` register in rapid succession will lose
one byte.
This can be observed by running `tests/drivers/spi/spi_loopback`.
The test will get stuck in `spi_sam0_fast_txrx()` forever waiting
for the final byte.
Undo this small optimisation and only load the next byte into the
`DATA` register after the response has been received.
This fixes `tests/drivers/spi/spi_loopback`.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
