Commit graph

42 commits

Author SHA1 Message Date
Yong Cong Sin 8f9ebb652f drivers: intc: plic: simplify isr handling
Save the reference of the start index of the `_sw_isr_table`
to the config struct, so that the `local_irq` can be used  as
offset directly.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-25 11:24:32 +03:00
Yong Cong Sin c5f5b964c1 arch: sw_isr: revamp multi-level interrupt architecture
Previously the multi-level irq lookup table is generated by
looping through the devicetree nodes using macros & Kconfig,
which is hard to read and flimsy.

This PR shifts the heavy lifting to devicetree & DT macros such
that an interrupt controller driver, which has its info in the
devicetree, can register itself directly with the multi-level
interrupt architecture, which is more straightforward.

The previous auto-generated look up table with macros is now
moved in a file of its own. A new compatibility Kconfig:
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is added and
enabled by default to compile the legacy look up table for
interrupt controller drivers that aren't updated to support the
new architecture yet.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-25 11:24:32 +03:00
Gerard Marull-Paretas 3381fb4b3d drivers: intc: plic: remove redundant include
<soc.h> is not needed.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-19 15:13:53 +00:00
Weiwei Guo eac50e318f drivers: intc_plic: fix plic PLIC_TRIG_LEVEL define mistake
Interrupt trigger type register each bit indicate the configured interrupt
type. bit value is 0 indicate level trigger interrupt, 1 indicate edge
trigger interrupt.

The level trigger defined to ~BIT(0) equal 0xfffffffe not equal 0.

Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
2024-01-10 10:01:23 +01:00
Gerard Marull-Paretas 0106e8d14c arch: riscv: introduce RISCV_PRIVILEGED
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.

Note that the SoC family naming scheme will be fixed in upcoming
commits.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
Yong Cong Sin dd7193e491 drivers: intc: plic: simplify the handling of the irq_count array
Store the compile-time computed length of the `irq_count` into
a variable so that we have less to do in runtime.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-08 12:35:52 +01:00
Yong Cong Sin 310c4539e9 drivers: intc: plic: fix compilation warning
Change the index variable type to `int` from `size_t` to compile
across 32bit and 64bit platforms without generating warnings.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-08 12:35:52 +01:00
Conor Paxton 7e192e9e27 drivers: intc_plic: claim interrupt from hart that serviced it
The plic has a very simple mechanism to claim an interrupt as well as to
complete and clear it. The same register is read from/ written to to
achieve this.

Get the ID of the HART that serviced the interrupt and write to the
claim complete register in the correct context
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
2023-12-12 10:56:20 +01:00
Conor Paxton 4e825f572c drivers: intc_plic: enable contexts for all harts on a platform
The plic uses contexts to seperate irq enables, threshold priority and
claim complete registers from each core for a given platform. As well as
this, each privilege level has its own context.
for multi-core platform's, we need to be able to enable/ disable a
global interrupt for all the cores that are associated with Zephyr.

To do this, we need to make some assumptions:
1. The privilege contexts are contiguous
2. M mode context is first, followed by S mode.

We know how many cpus are used in an application and each cpu's hartid,
thanks to some very handy inline functions. So we iterate through each
cpu and use the hartid of a cpu in the calculation of the context.

While we are at it, In an effort to make the driver more readable,
allign with the macro naming convention outlined in Linux's PLIC driver

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
2023-12-12 10:56:20 +01:00
Yong Cong Sin 0a3fe40505 drivers: intc: plic: set edge-triggered register address using compat
Define the edge-trigger register base address based on whether
the PLIC node in the devicetree has an additional compatible
that supports edge-triggered interrupt.

Limited the implementation to Andes NCEPLIC100 only, updated
the devicetree binding of `andes_v5_ae350` accordingly.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-12-08 07:51:05 -05:00
Yong Cong Sin e6f77f9b73 driver: intc: plic: fix trigger type register bit calculation
The bit position calculation for the trigger type is wrong,
fix that.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-30 10:04:43 +01:00
Wojciech Sipak 76c8bf0f7c drivers: interrupt_controller: intc_plic: rewrite get_plic_dev_from_irq
There's a ternary operator that depends on configuration-defined macro:
`CONFIG_DYNAMIC_INTERRUPTS` is not enabled by default
for any of the platforms that use PLIC,
it is possbile to set it to `=y` though.

This triggered the Coverity check to report it as dead code.

Fixes #65576.

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-11-29 10:09:48 +01:00
Yong Cong Sin cb10e94799 drivers: intc: plic: minor code refactor
The `riscv_plic_irq_enable` & `riscv_plic_irq_disable` are very
similar, refactor them out into `plic_irq_enable_set_state`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-25 08:51:52 -05:00
Yong Cong Sin e9fa6f8b4a drivers: intc: plic: add shell cmd to get irq stats for debugging
Introduced `CONFIG_PLIC_SHELL` to enable the build of shell
debugging command to get the hit count of each interrupt
controller's IRQ line. This is especially useful when working
with dynamically installed ISRs, which will be the case for
`plic_sw`.

Example usage:

```
uart:~$ plic stats get interrupt-controller@c000000
   IRQ        Hits
==================
    10         177

uart:~$ plic stats get interrupt-controller@c000000
   IRQ        Hits
==================
    10         236

uart:~$ plic stats clear interrupt-controller@c000000
Cleared stats of interrupt-controller@c000000.

uart:~$ plic stats get interrupt-controller@c000000
   IRQ        Hits
==================
    10          90

```

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Maxim Adelman <imax@meta.com>
2023-11-24 09:23:33 +01:00
Yong Cong Sin 8342d87478 drivers: intc: plic: brackets for if-conds & use explicit comparison
if-conditionals should have brackets according to Zephyr's
coding standard, and explicitly compares `edge_irq` against 0.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-24 09:23:33 +01:00
Piotr Wojnarowski 6670dbe834 tests: drivers: intc_plic: Add tests for register index and offset
Add a test to verify that the regression from
ffb8f31bff is fixed.

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-11-20 09:20:13 +01:00
Piotr Wojnarowski 3afe238926 drivers: intc: plic: Fix memory-mapped register offset calculation
Previously, the PLIC's registers were accessed through uint32_t *,
so all calculated offsets were effectively multiplied by
sizeof(uint32_t). Do the same manuallly now that we have
mem_addr_t/sys_read32.

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-11-20 09:20:13 +01:00
Piotr Wojnarowski 3ef34ff6d1 drivers: intc: plic: Make function names and types consistent
`get_claim_complete_offset` and `get_threshold_priority_offset` actually
return addresses directly. Rename them to `_addr` for consistency within
the driver. Also change their return type to `mem_addr_t`.

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-11-20 09:20:13 +01:00
Yong Cong Sin ffb8f31bff drivers: intc: plic: Use sys IO APIs to access memory-mapped registers
Use arch-specific sys IO APIs to access the memory-mapped
registers to ensure safe memory operations

fixes #62956

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 18:20:43 +01:00
Yong Cong Sin 980fb4b846 drivers: intc: plic: make sense of magic number
Added some defines and helper functions to help with the
arithmetics so that the bit shifts and stuff do not look like
magic number.

Converted manual bit shift/set/unset to use macros provided by
Zephyr.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 18:20:43 +01:00
Yong Cong Sin e538b0e5a6 drivers: plic: support multiple instances for multi-level
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 18:20:43 +01:00
Yong Cong Sin 76a7b3cf1c drivers: intc: plic: initial refactor for multi-instance support
Use a config struct to store per-instance device config during
init and connect the IRQ based on the devicetree instead of
hardcoded value and instance number.

The `get_plic_dev_from_irq` is still a placeholder for now and
always return the first instance.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-11-09 18:20:43 +01:00
Yong Cong Sin 39433f0669 drivers: intc: plic: define all registers' offset in the driver
Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.

Updated devicetrees that has PLIC accordingly.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-04 09:06:28 -04:00
Yong Cong Sin 8db1a5add2 drivers: intc: plic: support trigger type by default and hardcode offset
Removing the edge-trigger Kconfig as it is supported by default
in the RISCV PLIC specifications.

Define the edge-trigger register offset in the driver instead
of retrieving the value from devicetree as it is not something
configurable. The value 0x1080 is defined in Andes & Telink
datasheets.

Updated build_all testcase.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-04 09:06:28 -04:00
Fabio Baltieri 843f66f52d intc: plic: convert SYS_INIT to DEVICE_DT_INST_DEFINE
Convert SYS_INIT to DEVICE_DT_INST_DEFINE, this allows the build system
to track the device dependencies and ensure that the interrupt
controller is initialized before other devices using it.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-09-22 09:22:55 +02:00
Yong Cong Sin 7afbcdc619 drivers: intc: plic: fix the calculation of trig register
trig register should be independent of the `riscv,max-priority` property.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-18 20:35:22 +02:00
Joshua Lilly 67268f5cbd drivers: interrupt_controller: plic: support edge triggered interrupts
This adds a check and option for edge triggered interrupts

Signed-off-by: Joshua Lilly <jgl@meta.com>
2023-07-31 10:08:52 +02:00
Alexander Razinkov cb491cacad drivers: support 64-bit addresses from devicetree for PLIC, MTIMER, UART
Usage of 64-bit address constants from devicetree without
an UINT64_C wrapping macro results in the following warning
and the cut-off of the address value:

"warning: integer constant is so large that it is unsigned"

This change fixes such issue for PLIC, MTIMER and UART in case
they are used with some 64-bit RISC-V platforms

Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
2023-06-25 03:29:54 -04:00
Carlo Caione edd3437826 riscv: Rename Kconfig symbol to *_PRIVILEGED
Rename SOC_FAMILY_RISCV_PRIVILEGE to SOC_FAMILY_RISCV_PRIVILEGED because
the spec is "privileged".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-09 11:46:29 -04:00
Gerard Marull-Paretas a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Gerard Marull-Paretas 178bdc4afc include: add missing zephyr/irq.h include
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-17 22:57:39 +09:00
Carlo Caione 5d104f20ab riscv: Introduce API for CLIC and PLIC
Introduce a new interface for CLIC and PLIC to be used by the drivers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Gerard Marull-Paretas fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Maureen Helm 41634c82cc drivers: interrupt_controller: Refactor drivers to use shared init prio
Refactors interrupt controller drivers to use the shared driver class
initialization priority configuration, CONFIG_INTC_INIT_PRIORITY, to
allow configuring interrupt controller drivers separately from other
devices. This is similar to other driver classes.

The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEFAULT to preserve
the existing default initialization priority for most drivers.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-03-14 11:28:06 +01:00
Daniel Leung 975e257f2c drivers: interrupt_controller: remove @return doc for void funcs
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Tomasz Bursztyka 4dcfb5531c isr: Normalize usage of device instance through ISR
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs

This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.

Note that only the ISR passed to IRQ_CONNECT are of interest here.

In order to do so, the script fix_isr.py below is necessary:

from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os

cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
(
 const struct device *D = (const struct device *)P;
|
 const struct device *D = P;
)
 ...
}

@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
 const struct device *D;
 ...
(
 D = (const struct device *)P;
|
 D = P;
)
 ...
}

@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
 ...
}

@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);

@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
 ...
}

@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
 ...
}
"""

def find_isr(fn):
    db = []
    data = None
    start = 0

    try:
        with open(fn, 'r+') as f:
            data = str(mmap.mmap(f.fileno(), 0).read())
    except Exception as e:
        return db

    while True:
        isr = ""
        irq = data.find('IRQ_CONNECT', start)
        while irq > -1:
            p = 1
            arg = 1
            p_o = data.find('(', irq)
            if p_o < 0:
                irq = -1
                break;

            pos = p_o + 1

            while p > 0:
                if data[pos] == ')':
                    p -= 1
                elif data[pos] == '(':
                    p += 1
                elif data[pos] == ',' and p == 1:
                    arg += 1

                if arg == 3:
                    isr += data[pos]

                pos += 1

            isr = isr.strip(',\\n\\t ')
            if isr not in db and len(isr) > 0:
                db.append(isr)

            start = pos
            break

        if irq < 0:
            break

    return db

def patch_isr(fn, isr_list):
    if len(isr_list) <= 0:
        return

    for isr in isr_list:
        tmplt = cocci_template.replace('<!fn!>', isr)
        with open('/tmp/isr_fix.cocci', 'w') as f:
            f.write(tmplt)

        cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]

        subprocess.run(cmd)

def process_files(path):
    if path.is_file() and path.suffix in ['.h', '.c']:
        p = str(path.parent) + '/' + path.name
        isr_list = find_isr(p)
        patch_isr(p, isr_list)
    elif path.is_dir():
        for p in path.iterdir():
            process_files(p)

if len(sys.argv) < 2:
    print("You need to provide a dir/file path")
    sys.exit(1)

process_files(Path(sys.argv[1]))

And is run: ./fix_isr.py <zephyr root directory>

Finally, some files needed manual fixes such.

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Tomasz Bursztyka e18fcbba5a device: Const-ify all device driver instance pointers
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.

A coccinelle rule is used for this:

@r_const_dev_1
  disable optional_qualifier
@
@@
-struct device *
+const struct device *

@r_const_dev_2
 disable optional_qualifier
@
@@
-struct device * const
+const struct device *

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Kumar Gala a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Kumar Gala 020a899ec3 drivers: sifive: Convert sifive drivers to new DT_INST macros
Convert older DT_INST_ macro use in sifive drivers to the new
include/devicetree.h DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-26 16:06:09 -05:00
Kumar Gala 61d30ed927 drivers: intc: plic: convert to DT_INST defines
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Olof Johansson 3b733b5282 interrupt_controller: plic: use shared symbol for DT_*
miv already had it defined, but let's shorten the names and use
them in the driver. This also adds it for sifive-freedom.

Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06 13:28:21 -05:00
Tomasz Bursztyka c30600d4ab drivers/interrupt_controller: Adopt file naming as other drivers
Pattern being <domain>_<model>.<c/h>.
Here interrupt_controller as a domain would be far too long so
shortening it to "intc", as DTS does actually.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-12-18 21:49:46 +01:00
Renamed from drivers/interrupt_controller/plic.c (Browse further)