interrupt_controller: plic: use shared symbol for DT_*
miv already had it defined, but let's shorten the names and use them in the driver. This also adds it for sifive-freedom. Signed-off-by: Olof Johansson <olof@lixom.net>
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a6b3b616f5
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3b733b5282
3 changed files with 21 additions and 24 deletions
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@ -42,8 +42,7 @@ static int save_irq;
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void riscv_plic_irq_enable(u32_t irq)
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{
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u32_t key;
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volatile u32_t *en =
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(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
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volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
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key = irq_lock();
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en += (irq >> 5);
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@ -66,8 +65,7 @@ void riscv_plic_irq_enable(u32_t irq)
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void riscv_plic_irq_disable(u32_t irq)
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{
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u32_t key;
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volatile u32_t *en =
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(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
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volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
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key = irq_lock();
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en += (irq >> 5);
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@ -86,8 +84,7 @@ void riscv_plic_irq_disable(u32_t irq)
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*/
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int riscv_plic_irq_is_enabled(u32_t irq)
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{
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volatile u32_t *en =
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(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
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volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
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en += (irq >> 5);
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return !!(*en & (1 << (irq & 31)));
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@ -106,11 +103,10 @@ int riscv_plic_irq_is_enabled(u32_t irq)
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*/
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void riscv_plic_set_priority(u32_t irq, u32_t priority)
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{
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volatile u32_t *prio =
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(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
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volatile u32_t *prio = (volatile u32_t *)DT_PLIC_PRIO;
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if (priority > DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY)
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priority = DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY;
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if (priority > DT_PLIC_MAX_PRIO)
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priority = DT_PLIC_MAX_PRIO;
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prio += irq;
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*prio = priority;
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@ -134,7 +130,7 @@ int riscv_plic_get_irq(void)
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static void plic_irq_handler(void *arg)
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{
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volatile struct plic_regs_t *regs =
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(volatile struct plic_regs_t *) DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;
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(volatile struct plic_regs_t *) DT_PLIC_REG;
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u32_t irq;
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struct _isr_table_entry *ite;
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@ -179,12 +175,10 @@ static int plic_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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volatile u32_t *en =
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(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
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volatile u32_t *prio =
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(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
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volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
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volatile u32_t *prio = (volatile u32_t *)DT_PLIC_PRIO;
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volatile struct plic_regs_t *regs =
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(volatile struct plic_regs_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS;
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(volatile struct plic_regs_t *)DT_PLIC_REG;
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int i;
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/* Ensure that all interrupts are disabled initially */
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@ -2,14 +2,10 @@
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/* PLIC */
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#define DT_PLIC_MAX_PRIORITY \
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DT_SIFIVE_PLIC_1_0_0_40000000_RISCV_MAX_PRIORITY
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#define DT_PLIC_PRIO_BASE_ADDR \
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DT_SIFIVE_PLIC_1_0_0_40000000_PRIO_BASE_ADDRESS
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#define DT_PLIC_IRQ_EN_BASE_ADDR \
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DT_SIFIVE_PLIC_1_0_0_40000000_IRQ_EN_BASE_ADDRESS
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#define DT_PLIC_REG_BASE_ADDR \
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DT_SIFIVE_PLIC_1_0_0_40000000_REG_BASE_ADDRESS
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#define DT_PLIC_MAX_PRIO DT_SIFIVE_PLIC_1_0_0_40000000_RISCV_MAX_PRIORITY
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#define DT_PLIC_PRIO DT_SIFIVE_PLIC_1_0_0_40000000_PRIO_BASE_ADDRESS
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#define DT_PLIC_IRQ_EN DT_SIFIVE_PLIC_1_0_0_40000000_IRQ_EN_BASE_ADDRESS
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#define DT_PLIC_REG DT_SIFIVE_PLIC_1_0_0_40000000_REG_BASE_ADDRESS
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/* UART 0 */
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#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS
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7
soc/riscv/riscv-privilege/sifive-freedom/dts_fixup.h
Normal file
7
soc/riscv/riscv-privilege/sifive-freedom/dts_fixup.h
Normal file
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@ -0,0 +1,7 @@
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/* SPDX-License-Identifier: Apache-2.0 */
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/* Copyright (c) 2020 Olof Johansson <olof@lixom.net> */
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#define DT_PLIC_MAX_PRIO DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY
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#define DT_PLIC_PRIO DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS
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#define DT_PLIC_IRQ_EN DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS
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#define DT_PLIC_REG DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS
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