Usage:
gpio info [device]
The new command prints gpio controller information
for a specific device if specified or if no device is specified
it prints out all controller information ordered by line name.
Also added Kconfig option so this command can be removed if
resources need to be conserved.
Signed-off-by: Nick Ward <nix.ward@gmail.com>
This commit implements this enhancement:
https://github.com/zephyrproject-rtos/zephyr/issues/63018
The forms of the gpio commands are now:
gpio conf device pin ol0
gpio set device pin 1
gpio get device pin
gpio blink device pin
Device name and pin subcommands now are
suggested/completed when tab is used.
Pin names are suggested with numbers and line names if
available from the gpio controller’s Devicetree node.
GPIO pin command is now limited to pins that are not assigned
as reserved.
Signed-off-by: Nick Ward <nix.ward@gmail.com>
Add Renesas rzt2m gpio driver with basic functionality.
It supports pin mode configuration and writing/reading to/from gpio ports.
Includes dts changes to build blinky sample.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Add pinctrl to the Davinci GPIO driver to allow muxing pins dirctly
in this driver.
Also aligned the macro backslashes as line continuation character at
the end of each line with each at the same position and removed the
GPIO_DAVINCI_DEVICE_INIT macro which seems to be not used.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
If the gpio had pull previous enabled, but new config
request wants the pull disabled, the code was failing
to clear the previous pull setting.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Move the syscall_handler.h header, used internally only to a dedicated
internal folder that should not be used outside of Zephyr.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add initial support for Renesas RA GPIO.
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
The multi-level encoding of the interrupt number currently
happens in the `gen_defines.py`, which is called in the
`dts.cmake` module after `kconfig.cmake`. However, the number
of bits used by each level is defined in Kconfig and this means
that `gen_defines.py` will not be able to get that information
during build.
To fix this, do the multi-level encoding in C devicetree macro
magic instead of the python script. This ticks one of a
long-standing TODO item from the `gen_defines.py`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Relocate multi-level interrupts APIs out of `irq.h` into
a new file named `irq_multilevel.h` to provide cleaner
separation between typical irq & multilevel ones.
Added preprocessor versions of `irq_to_level_x` as `IRQ_TO_Lx`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
To avoid glitches when configuring GPIO output, make logic closer to
that of V2 after 79ee5a876f.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
The BCM2711 SoC exposes 58 GPIOs. The first 28 (bank 0) are accessible
to users via the 40-pin header, while the others (bank 1) are used for
controlling on-board peripherals.
This also update doc of `rpi_4b` board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Extend the NXP S32 GPIO driver to be able to route external interrupts
to either SIUL2 EIRQ interrupt controller or, when available on the
SoC, WKPU interrupt controller.
Since WKPU can support up to 64 external interrupt sources and SIUL2
EIRQ up to 32, gpio_get_pending_int() is removed and the interrupt
controller specific API must be used instead.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The number of IRQ first level bits is not necessarily 8 bits
now, so use `CONFIG_1ST_LEVEL_INTERRUPT_BITS` instead of
hardcoded value.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
NOCACHE_MEMORY depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT, so
don't try to select the symbol if not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Change introduces a new configuration option that can be used to disable
GPIO interrupt support to reduce memory footprint.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
This commit resolves an internal dependecy between GET_DIRECTION and
GET_CONFIG configuration. GET_CONFIG api is internally needed by
GET_DIRECTION api.
Signed-off-by: Martin Kiepfer <m.kiepfer@teleschirm.org>
The Nuvoton NCT38xx is a multi-function device providing a TCPC
controller and a I/O expander (GPIO driver). Add a multi-function
driver to manage exclusive access to the device.
Tested with "twister -T tests/drivers/build_all/gpio".
Signed-off-by: Keith Short <keithshort@google.com>
Only provide implementations for optional operations if needed. This
patch deletes quite a few dummy `pin_interrupt_configure` ops (now
optional), and adjusts ifdeffery on some drivers so that optional ops
are only provided if they implement real functionality.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This change allows to have GPIO interrupts configured
that will work while chip enters low power modes where
PD_COM is turned off.
PDC controller can wake up system on GPIO changes even when
PD_COM is off.
This is done by adding PDC entries that will wakeup Cortex-M33
at the same time when WAKEUP controller is programmed to
handle GPIO state changes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Hardware supports only one edge for GPIO interrupt.
This adds software implementation that hides hardware restriction.
With this change user code can use GPIO_INT_TRIG_BOTH and does not
have to do it in application code.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Init level for GPIO drivers is set PRE_KERNEL_1.
Smartbond(tm) driver had it set to POST_KERNEL by accident.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Davinci gpio controller support to add various soc gpio
support (J721E, AM654).
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
GPIO: section 12.1.2
BeagleBone AI_64 https://beagleboard.org/ai-64
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Current setup tries to initialize the bank driver before the parent one,
which is the inverse of what the devicetree hierarchy implies and
causes a bunch of:
ERROR: /soc/gpio@e000a000/psgpio_bank@3 PRE_KERNEL_1 40 32 <
/soc/gpio@e000a000 PRE_KERNEL_2 40 10
Change the bank driver to initialize at PRE_KERNEL_1 as the parent
drivers so that ordinals take care of priority between these two.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This gpio data register and keyboard scan out register are shared
register. To prevent race condition caused by access from different
thread, add critical section.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Increase the default init priority of nct38xx so that they work well
with the default I2C init priority (50).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
AXP192 is a small power management IC, that also
features 5 GPIOS.
Besides GPIO driver this commit also includes needed modifications
in axp192 regulator and mfd driver as LDOIO0 functioanlity
is multiplexed with GPIO0 pin.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
