This gpio data register and keyboard scan out register are shared
register. To prevent race condition caused by access from different
thread, add critical section.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Increase the default init priority of nct38xx so that they work well
with the default I2C init priority (50).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
AXP192 is a small power management IC, that also
features 5 GPIOS.
Besides GPIO driver this commit also includes needed modifications
in axp192 regulator and mfd driver as LDOIO0 functioanlity
is multiplexed with GPIO0 pin.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Implement `gpio_pin_get_config` for the stellaris platform, and by
extension `qemu_cortex_m3`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Implement `gpio_pin_get_config` for the stellaris platform, and by
extension `qemu_cortex_m3`.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Interrupt callbacks may want to configure GPIO pins on the port expander,
e.g. to change the polarity of a level interrupt. This would cause a
deadlock because the callback handler would still be holding the lock.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
memcpy of a sub-structure in a structure was using the structure size
of the parent structure instead of the sub-structure.
fixes: #59548
Signed-off-by: David Leach <david.leach@nxp.com>
gpio_nrfx_port_get_direction() is meant to check which inputs
are enabled, and does so by checking one bit at a time
and setting that bit into the "input" parameter.
But "input" was never zeroed, so any garbage ones it
may have remains.
Zero it.
This fixes a problem where if the "input" parameter was not
zeroed by the caller, the result of the funcion call
is undefined.
Detected by valgrind on:
tests/drivers/gpio/gpio_get_direction
Conditional jump or move depends on uninitialised value(s)
by gpio_get_direction_test_disconnect (main.c:64)
Conditional jump or move depends on uninitialised value(s)
by gpio_get_direction_test_output (main.c:102)
When running this test for the nrf52_bsim.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Split the SDL GPIO emulator driver in a top and bottom
to enable using it with embedded libCs.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The blink command should blink until the user presses a key, however on
some systems a pending keypress is present when entering the loop
causing it to immediate exit before getting a chance to blink.
Add a dummy read to clear the buffer before starting the blink loop.
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
To ease building for workstation tests, instead of using
the ARM CMSIS instructions instrinsics directly,
use the NRFX macro that uses the compiler builtins when
necessary.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Instead of getting the hardcoded address from the DT structure
use its symbolic name (Also from DT) which will be resolved
by the nRF HAL definitions.
This allows the GPIO peripherals' addresses to be redefined
for the simulated targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Guard NXP PINT related code with #ifdef CONFIG_NXP_PINT.
This prevents build errors on platforms that do not have a PINT but have
LPC GPIO.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Local register read/write functions have been removed and replaced
with calls to the new MFD functions.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
Add memory mapping to driver in order to use driver with platforms based
on Cortex A with enabled MMU.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Check the return value from gpio_add_callback() and fail driver
initialization if non-zero.
Fixes: #58584
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This makes Kconfig logging options for this driver depending on whether
the driver is enabled or not.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Basically, once a pin is configured for interrupt, we enable the latch
on it, in order not to miss short pulses.
The bottom half of the interrupt then reads the input port twice, to
read the latch and then read the potentially new state of the pins, to
compute the posedge, negedge, and level callbacks accordingly.
Signed-off-by: Vincent Geneves <vgeneves@kalray.eu>
When accessing GPIO by pin, access only the required port register
(instead of systematically accessing both PORT0 and PORT1).
Signed-off-by: Vincent Geneves <vgeneves@kalray.eu>
Clean up whitespace etc. using clang-format after previous changes. No
functional changes intended.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Added support for interrupt-driven GPIO for this driver if an interrupt
line is defined. Note that interrupt support is optional in the GPIO
core so it may or may not be present.
The core provides a single state change notification whenever any line
changes state on a given bank, so we need to check the states of the
lines ourselves to determine what has actually changed.
Also, the driver treats the first and second GPIO banks as mostly
separate devices, but a single interrupt is shared by both banks, so the
ISR ends up being registered by the first bank which also triggers
handling on the second bank if required.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The properties being read for the all-inputs and all-outputs flags in
the driver for the second GPIO channel did not match the ones listed in
the DT schema or the existing device tree files. Fix this.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Make sure MFD driver for nPM6001 gets built, and, that GPIO driver comes
later in the init sequence.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Status readback has been added in the latest silicon revision.
.port_get_raw and .port_toggle_bits are now supported
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
A glitch was observed if a GPIO PIN was configured to a
non-default state by ROM and then Zephyr programs the pin
for the same configuration. Root cause is GPIO hardware
implementing two output bits for each pin. The alternate
output bit is in the pin control register and is r/w by
default. The other bit exists in the GPIO parallel ouput
register and is read-only by default. The hardware actually
reflects the pin's output value into both bits. The fix is
to configure the pin with alternate output bit read-write
and the last step is to disable alternate output which
enabled read-write of the parallel bit. GPIO API's can
then use the GPIO parallel out registers. Add logic to
return an error from the GPIO interrupt configure API if
a pin is not configured as an input. Hardware only performs
interrupt detection if the input pad is enabled.
Hardware supports a pin being configured for both input
and output. Applications should add the GPIO_INPUT flag
to all pin configuration requiring interrupt detection.
The interpretation of input and output flags for the
get configuration API appears to be only one of the
flags can be set. Please refer to the GPIO driver tests.
Updated GPIO interrupt configure to clear the input pad
disable bit due to interrupt detection HW is connected
only to input side of pin.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add Port 14/15 to device tree. These ports can only be configured as input.
Error out in gpio driver if user sets them as output.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The iMX platform always uses pinctrl, there's no need to keep
extra macrology around pinctrl. Also updated driver's Kconfig to `select
PINCTRL`.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The MCUX platform always uses pinctrl, there's no need to keep extra
macrology around pinctrl. Also updated driver's Kconfig options to
`select PINCTRL` (note that some already did).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
